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    Thermoelectric device and method for fabricating the same
    1.
    发明授权
    Thermoelectric device and method for fabricating the same 有权
    热电装置及其制造方法

    公开(公告)号：US08940995B2

    公开(公告)日：2015-01-27

    申请号：US12632403

    申请日：2009-12-07

    申请人： Young-Sam Park ,  Moon-Gyu Jang ,  Taehyoung Zyung ,  Younghoon Hyun ,  Myungsim Jun

    发明人： Young-Sam Park ,  Moon-Gyu Jang ,  Taehyoung Zyung ,  Younghoon Hyun ,  Myungsim Jun

    IPC分类号： H01L35/12 ,  H01L35/32

    CPC分类号： H01L35/32 ,  H01L35/26 ,  H01L35/34

    摘要： A thermoelectric device is provided. The thermoelectric device includes first and second electrodes, a first leg, a second leg, and a common electrode. The first leg is disposed on the first electrode and includes one or more first semiconductor pattern and one or more first barrier patterns. The second leg is disposed on the second electrode and includes one or more second semiconductor pattern and one or more second barrier patterns. The common electrode is disposed on the first leg and the second leg. Herein, the first barrier pattern has a lower thermal conductivity than the first semiconductor pattern, and the second barrier pattern has a lower thermal conductivity than the second semiconductor pattern. The first/second barrier pattern has a higher electric conductivity than the first/second semiconductor pattern. The first/second barrier pattern forms an ohmic contact with the first/second semiconductor pattern.

    摘要翻译： 提供了一种热电装置。 热电装置包括第一和第二电极，第一支腿，第二支腿和公共电极。 第一支腿设置在第一电极上并且包括一个或多个第一半导体图案和一个或多个第一屏障图案。 第二腿设置在第二电极上，并且包括一个或多个第二半导体图案和一个或多个第二屏障图案。 公共电极设置在第一腿部和第二腿部上。 这里，第一阻挡图案的热导率比第一半导体图案低，第二阻挡图案的热导率比第二半导体图案低。 第一/第二阻挡图案具有比第一/第二半导体图案更高的导电性。 第一/第二屏障图案与第一/第二半导体图案形成欧姆接触。

    THERMOELECTRIC DEVICE AND METHOD FOR FABRICATING THE SAME
    2.
    发明申请
    THERMOELECTRIC DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    热电装置及其制造方法

    公开(公告)号：US20110000517A1

    公开(公告)日：2011-01-06

    申请号：US12632403

    申请日：2009-12-07

    申请人： Young-Sam Park ,  Moon-Gyu Jang ,  Taehyoung Zyung ,  Younghoon Hyun ,  Myungsim Jun

    发明人： Young-Sam Park ,  Moon-Gyu Jang ,  Taehyoung Zyung ,  Younghoon Hyun ,  Myungsim Jun

    IPC分类号： H01L35/20 ,  H01L35/00 ,  B05D5/12 ,  H01L35/34

    CPC分类号： H01L35/32 ,  H01L35/26 ,  H01L35/34

    摘要： A thermoelectric device is provided. The thermoelectric device includes first and second electrodes, a first leg, a second leg, and a common electrode. The first leg is disposed on the first electrode and includes one or more first semiconductor pattern and one or more first barrier patterns. The second leg is disposed on the second electrode and includes one or more second semiconductor pattern and one or more second barrier patterns. The common electrode is disposed on the first leg and the second leg. Herein, the first barrier pattern has a lower thermal conductivity than the first semiconductor pattern, and the second barrier pattern has a lower thermal conductivity than the second semiconductor pattern. The first/second barrier pattern has a higher electric conductivity than the first/second semiconductor pattern. The first/second barrier pattern forms an ohmic contact with the first/second semiconductor pattern.

    摘要翻译： 提供了一种热电装置。 热电装置包括第一和第二电极，第一支腿，第二支腿和公共电极。 第一支腿设置在第一电极上并且包括一个或多个第一半导体图案和一个或多个第一屏障图案。 第二腿设置在第二电极上，并且包括一个或多个第二半导体图案和一个或多个第二屏障图案。 公共电极设置在第一腿部和第二腿部上。 这里，第一阻挡图案的热导率比第一半导体图案低，第二阻挡图案的热导率比第二半导体图案低。 第一/第二阻挡图案具有比第一/第二半导体图案更高的导电性。 第一/第二屏障图案与第一/第二半导体图案形成欧姆接触。

    Method for fabricating Schottky barrier tunnel transistor
    6.
    发明授权
    Method for fabricating Schottky barrier tunnel transistor 失效
    制造肖特基势垒隧道晶体管的方法

    公开(公告)号：US07745316B2

    公开(公告)日：2010-06-29

    申请号：US11930902

    申请日：2007-10-31

    申请人： Yark-Yeon Kim ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

    发明人： Yark-Yeon Kim ,  Seong-Jae Lee ,  Moon-Gyu Jang ,  Tae-Youb Kim ,  Chel-Jong Choi ,  Myung-Sim Jun ,  Byoung-Chul Park

    IPC分类号： H01L21/28 ,  H01L21/44

    CPC分类号： H01L29/78618 ,  H01L29/7839

    摘要： Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.

    摘要翻译： 提供一种用于制造肖特基势垒隧道晶体管（SBTT）的方法，其可以从根本上防止由栅极电极的两个侧壁上形成的间隔物的损坏引起的栅极漏电流的产生。 一种制造肖特基势垒隧道晶体管的方法，包括：a）在由支撑衬底支撑的掩埋氧化物层上形成硅图案和牺牲图案; b）在暴露于硅图案的两侧的掩埋氧化物层上形成源极/漏极区域，源极/漏极区域由金属层形成并与硅图案的两个侧壁接触; c）去除牺牲图案以暴露硅图案的顶表面; 以及d）在暴露的硅图案上形成栅极绝缘层和栅电极。

    Schottky barrier tunnel transistor using thin silicon layer on insulator and method for fabricating the same
    7.
    发明授权
    Schottky barrier tunnel transistor using thin silicon layer on insulator and method for fabricating the same 失效
    使用绝缘体上的薄硅层的肖特基势垒隧道晶体管及其制造方法

    公开(公告)号：US06693294B1

    公开(公告)日：2004-02-17

    申请号：US10331945

    申请日：2002-12-31

    申请人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

    发明人： Moon-Gyu Jang ,  Seong-Jae Lee ,  Woo-Seok Cheong ,  Won-Ju Cho ,  Kyoung-Wan Park

    IPC分类号： H01L3900

    CPC分类号： H01L29/42384 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/78609 ,  H01L29/78696

    摘要： Provided are a Schottky barrier tunnel transistor (SBTT) and a method of fabricating the same. The SBTT includes a buried oxide layer formed on a base substrate layer and having a groove at its upper surface; an ultra-thin silicon-on-insulator (SOI) layer formed across the groove; an insulating layer wrapping the SOI layer on the groove; a gate formed to be wider than the groove on the insulating layer; source and drain regions each positioned at both sides of the gate, the source and drain regions formed of silicide; and a conductive layer for filling the groove. In the SBTT, the SOI layer is formed to an ultra-thin thickness to minimize the occurrence of a leakage current, and a channel in the SOI layer below the gate is completely wrapped by the gate and the conductive layer, thereby improving the operational characteristics of the SBTT.

    摘要翻译： 提供了一种肖特基势垒隧道晶体管（SBTT）及其制造方法。 SBTT包括形成在基底层上并在其上表面具有凹槽的掩埋氧化物层; 跨越沟槽形成的超薄绝缘体上硅（SOI）层; 将SOI层包裹在槽上的绝缘层; 形成为比绝缘层上的沟槽宽的栅极; 源极和漏极区域各自位于栅极的两侧，源极和漏极区域由硅化物形成; 以及用于填充凹槽的导电层。 在SBTT中，SOI层形成为超薄的厚度，以最小化泄漏电流的发生，栅极下方的SOI层中的沟道被栅极和导电层完全包围，从而提高了操作特性 的SBTT。

    THERMOELECTRIC DEVICE, THERMOELECTIC DEVICE MODULE, AND METHOD OF FORMING THE THERMOELECTRIC DEVICE
    8.
    发明申请
    THERMOELECTRIC DEVICE, THERMOELECTIC DEVICE MODULE, AND METHOD OF FORMING THE THERMOELECTRIC DEVICE 审中-公开
    热电装置，热电装置模块及形成热电装置的方法

    公开(公告)号：US20120152296A1

    公开(公告)日：2012-06-21

    申请号：US13408153

    申请日：2012-02-29

    申请人： Moon-Gyu Jang ,  Myung-Sim Jun ,  Tae-Moon Roh ,  Jong-Dae Kim ,  Tae-Hyoung Zyung

    发明人： Moon-Gyu Jang ,  Myung-Sim Jun ,  Tae-Moon Roh ,  Jong-Dae Kim ,  Tae-Hyoung Zyung

    IPC分类号： H01L35/28 ,  H01L35/34 ,  B82Y99/00 ,  B82Y40/00

    CPC分类号： H01L35/32 ,  H01L35/34

    摘要： Provided are a thermoelectric device, a thermoelectric device module, and a method of forming the thermoelectric device. The thermoelectric device includes a first conductive type first semiconductor nanowire including at least one first barrier region; a second conductive type second semiconductor nanowire including at least one second barrier region; a first electrode connected to one end of the first semiconductor nanowire; a second electrode connected to one end of the second semiconductor nanowire; and a common electrode connected to the other end of the first semiconductor nanowire and the other end of the second semiconductor nanowire. The first barrier region is greater than the first semiconductor nanowire in thermal conductivity, and the second barrier region is greater than the second semiconductor nanowire in thermal conductivity.

    摘要翻译： 提供了一种热电装置，热电装置模块和形成热电装置的方法。 热电装置包括：第一导电型第一半导体纳米线，其包括至少一个第一阻挡区; 包括至少一个第二阻挡区域的第二导电类型的第二半导体纳米线; 连接到第一半导体纳米线的一端的第一电极; 连接到所述第二半导体纳米线的一端的第二电极; 以及连接到第一半导体纳米线的另一端和第二半导体纳米线的另一端的公共电极。 第一阻挡区域的导热率大于第一半导体纳米线，第二阻挡区域的导热率大于第二半导体纳米线。

    Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device by using the same
    10.
    发明申请
    Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device by using the same 审中-公开
    半导体装置的制造装置及其制造方法

    公开(公告)号：US20060048706A1

    公开(公告)日：2006-03-09

    申请号：US10527056

    申请日：2002-12-30

    申请人： Woo-Seok Cheong ,  Seong-Jae Lee ,  Won-Ju Jo ,  Moon-Gyu Jang

    发明人： Woo-Seok Cheong ,  Seong-Jae Lee ,  Won-Ju Jo ,  Moon-Gyu Jang

    IPC分类号： C23C16/00

    CPC分类号： H01L21/67207 ,  H01L29/66848

    摘要： In a process for manufacturing a hyperfine semiconductor device, an apparatus for manufacturing a semiconductor device such as a schottky barrier MOSFET and a method for manufacturing the semiconductor device using the same are provided. Two chambers are connected with each other. A cleaning process, a metal layer forming process, and subsequent processes can be performed in situ by using the two chambers, thereby the attachment of the unnecessary impurities and the formation of the oxide can be prevented and the optimization of the process can be accomplished.

    摘要翻译： 在制造超精细半导体器件的方法中，提供了用于制造诸如肖特基势垒MOSFET的半导体器件的装置以及使用其制造半导体器件的方法。 两个腔室相互连接。 可以通过使用两个室来原位进行清洁处理，金属层形成工艺和随后的工艺，从而可以防止不必要的杂质的附着和氧化物的形成，并且可以实现工艺的优化。