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43 条记录 (耗时 0.031 秒)

    Method of manufacturing a metal oxide semiconductor transistor
    1.
    发明授权
    Method of manufacturing a metal oxide semiconductor transistor 有权
    制造金属氧化物半导体晶体管的方法

    公开(公告)号：US06913979B2

    公开(公告)日：2005-07-05

    申请号：US10427164

    申请日：2003-04-30

    申请人： Young-Sub You ,  Hyeon-Deok Lee ,  Tae-Soo Park ,  Heon-Heoung Leam ,  Bong-Hyun Kim ,  Yong-Woo Hyung

    发明人： Young-Sub You ,  Hyeon-Deok Lee ,  Tae-Soo Park ,  Heon-Heoung Leam ,  Bong-Hyun Kim ,  Yong-Woo Hyung

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L21/823418 ,  H01L21/823425

    摘要： Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.

    摘要翻译： 公开了一种具有增强的可靠性的制造MOS晶体管的方法。 在栅电极和基板上形成钝化层，以防止在基板上产生凹陷。 在衬底上形成用于掩蔽衬底的一部分的掩模图案之后，将杂质注入到衬底的暴露部分中以形成源区和漏区。 冲洗衬底，使得钝化层或凹陷预防层基本上完全或部分去除，同时掩模图案被基本上完全去除，从而形成MOS晶体管。 因此，在衬底漂洗期间由于钝化层可以防止在衬底的源区和漏区中产生凹陷。

    Recessed gate electrode and method of forming the same and semiconductor device having the recessed gate electrode and method of manufacturing the same
    2.
    发明授权
    Recessed gate electrode and method of forming the same and semiconductor device having the recessed gate electrode and method of manufacturing the same 有权
    嵌入式栅电极及其形成方法以及具有凹陷栅电极的半导体器件及其制造方法

    公开(公告)号：US07563677B2

    公开(公告)日：2009-07-21

    申请号：US11531239

    申请日：2006-09-12

    申请人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

    发明人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung Kim ,  Jung-Hwan Oh ,  Young-Sub You

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

    摘要： A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

    摘要翻译： 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于第二多晶硅层中的杂质，可以基本上防止第二凹陷内的空隙的迁移。

    RECESSED GATE ELECTRODE AND METHOD OF FORMING THE SAME AND SEMICONDUCTOR DEVICE HAVING THE RECESSED GATE ELECTRODE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    RECESSED GATE ELECTRODE AND METHOD OF FORMING THE SAME AND SEMICONDUCTOR DEVICE HAVING THE RECESSED GATE ELECTRODE AND METHOD OF MANUFACTURING THE SAME 有权
    残留门电极及其制造方法和具有阻挡栅极电极的半导体器件及其制造方法

    公开(公告)号：US20070059889A1

    公开(公告)日：2007-03-15

    申请号：US11531239

    申请日：2006-09-12

    申请人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung KIM ,  Jung-Hwan OH ,  Young-Sub You

    发明人： Dae-Han Yoo ,  Kong-Soo Lee ,  Chang-Hoon Lee ,  Yong-Woo Hyung ,  Hyeon-Deok Lee ,  Hyo-Jung KIM ,  Jung-Hwan OH ,  Young-Sub You

    IPC分类号： H01L21/336

    CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

    摘要： A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to the presence of impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.

    摘要翻译： 凹陷栅极电极结构包括第一凹部和与形成在基板中的第一凹部连通的第二凹部。 第二凹部比第一凹部大。 栅极电介质层形成在基板的顶表面上和第一凹槽和第二凹槽的内表面上。 第一多晶硅层填充第一凹槽并以第一杂质密度掺杂杂质。 第二多晶硅层填充第二凹槽，并以第二杂质密度掺杂杂质。 在第二多晶硅层内限定空隙。 在栅极电介质和第一多晶硅层上形成第三多晶硅层，并以第三杂质密度掺杂杂质。 由于在第二多晶硅层中存在杂质，可以基本上防止第二凹陷内的空隙的迁移。

    Method of forming a gate of a non-volatile memory device
    7.
    发明授权
    Method of forming a gate of a non-volatile memory device 失效
    形成非易失性存储器件的栅极的方法

    公开(公告)号：US07008844B2

    公开(公告)日：2006-03-07

    申请号：US10635969

    申请日：2003-08-06

    申请人： Bong-Hyun Kim ,  Hun-Hyeoung Lim ,  Hyeon-Deok Lee ,  Yong-Woo Hyung

    发明人： Bong-Hyun Kim ,  Hun-Hyeoung Lim ,  Hyeon-Deok Lee ,  Yong-Woo Hyung

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273

    摘要： A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.

    摘要翻译： 在半导体器件上形成隧道介电层。 在隧道介电层上形成浮栅层。 在浮栅层上形成隔间介电层（ONO层）。 在栅间电介质层上沉积原位掺杂硅以形成控制栅层，然后进行退火。 通过光刻工艺对控制栅极层，隔间电介质层和浮栅层进行构图。 在随后的栅极氧化工艺期间不会发生控制栅极硅层的相变，以减小ONO层的厚度变化，从而提高半导体器件的耐久性和烘烤保持特性。