公开(公告)号：US06177316B1

公开(公告)日：2001-01-23

申请号：US09412278

申请日：1999-10-05

申请人： Yue-Song He ,  Kent K. Chang ,  John J. Wang

发明人： Yue-Song He ,  Kent K. Chang ,  John J. Wang

IPC分类号： H01L21336

CPC分类号： H01L21/28273

摘要： An improved method for fabricating a NAND-type memory cell structure. The present invention forgoes providing a contact mask implantation process prior to deposition of a metal barrier layer, which is a typical order of processing the NAND-type memory cell. Instead, in the present invention, the metal barrier layer is deposited on a core area of the NAND-type memory cell prior to contact mask implantation. Thereafter, the contact mask implantation process is performed on the structure in a conventional manner.

摘要翻译： 一种用于制造NAND型存储单元结构的改进方法。 本发明放弃在沉积金属阻挡层之前提供接触掩模注入工艺，这是处理NAND型存储单元的典型顺序。 相反，在本发明中，在接触掩模植入之前，将金属阻挡层沉积在NAND型存储单元的核心区域上。 此后，以常规方式对结构进行接触掩模注入工艺。

公开(公告)号：US06979619B1

公开(公告)日：2005-12-27

申请号：US09941370

申请日：2001-08-28

申请人： Hao Fang ,  Yue-Song He ,  Mark S. Chang ,  Kent K. Chang

发明人： Hao Fang ,  Yue-Song He ,  Mark S. Chang ,  Kent K. Chang

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11543

摘要： In a first aspect of the present invention, a method of fabricating a flash memory device is disclosed. The method comprises the steps of providing a portion of a dual gate oxide in a periphery area of the memory device and then simultaneously providing a dual gate oxide in a core area of the memory device and completing the dual gate oxide in the periphery area. Finally, a nitridation process is provided in both the core and periphery areas subsequent to the previous steps. In a second aspect of the present invention, a flash memory device is disclosed. The flash memory device comprises core area having a plurality of memory transistors comprising an oxide layer, a first poly layer, an interpoly dielectric layer, and a second poly layer. The flash memory device further comprises a periphery area having a plurality of transistors comprising an oxide layer, a portion of the first poly layer, and the second poly layer. According to the present invention, the method for fabricating the flash memory device is a simplified process that results in a significant improvement in the oxide reliability in the core and periphery areas and also eliminates the nitrogen contamination problem in the periphery area.

摘要翻译： 在本发明的第一方面中，公开了一种制造闪速存储器件的方法。 该方法包括以下步骤：在存储器件的外围区域中提供双栅极氧化物的一部分，然后在存储器件的核心区域中同时提供双栅极氧化物，并在周边区域中完成双栅极氧化物。 最后，在上述步骤之后，在核心区域和外围区域都提供氮化处理。 在本发明的第二方面，公开了一种闪速存储器件。 闪存器件包括具有包括氧化物层，第一多晶硅层，多晶硅间介电层和第二多晶硅层的多个存储晶体管的核心区域。 闪存器件还包括具有包括氧化物层，第一多晶硅层的一部分和第二多晶硅层的多个晶体管的外围区域。 根据本发明，用于制造闪速存储器件的方法是简化的工艺，其显着提高了芯部和外围区域中的氧化物可靠性，并且还消除了周边区域中的氮污染问题。

公开(公告)号：US6153470A

公开(公告)日：2000-11-28

申请号：US374059

申请日：1999-08-12

申请人： Yue-Song He ,  Kent K. Chang ,  Jiahua Huang

发明人： Yue-Song He ,  Kent K. Chang ,  Jiahua Huang

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/72 ,  H01L31/072

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/4916 ,  Y10S438/923

摘要： A method of forming floating gate to improve tunnel oxide reliability for flash memory devices. A substrate having a source, drain, and channel regions is provided. A tunnel oxide layer is formed over the substrate. A floating gate is formed over the tunnel oxide and the channel region, the floating gate being multi-layered and having a second layer sandwiched between a first layer and a third layer. The first layer of the floating gate overlying the tunnel oxide layer includes an undoped or lightly doped material. The second layer is highly-doped. The third layer is in direct contact with a dielectric layer, e.g., an oxide-nitride-oxide stack, and is made of an undoped or lightly doped material. A dielectric material is formed over the floating gate and a control gate is formed over the dielectric material.

摘要翻译： 一种形成浮动栅极以提高闪存器件的隧道氧化物可靠性的方法。 提供具有源极，漏极和沟道区域的衬底。 在衬底上形成隧道氧化物层。 在隧道氧化物和沟道区域上形成浮栅，浮栅是多层的，并且具有夹在第一层和第三层之间的第二层。 覆盖隧道氧化物层的浮置栅极的第一层包括未掺杂或轻掺杂的材料。 第二层是高度掺杂的。 第三层与电介质层直接接触，例如氧化物 - 氮化物 - 氧化物堆叠，并且由未掺杂或轻掺杂的材料制成。 介电材料形成在浮动栅极上，并且控制栅极形成在电介质材料上。

公开(公告)号：US07816726B2

公开(公告)日：2010-10-19

申请号：US11961183

申请日：2007-12-20

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42344

摘要： Charge-trapping dielectric (160) in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

摘要翻译： 非易失性存储单元中的电荷俘获电介质（160）从控制栅极的边缘和/或从衬底隔离区域的边缘凹陷。 凹入的几何形状用于减少或消除电荷难以擦除的区域中的电荷捕获。

公开(公告)号：US20090184359A1

公开(公告)日：2009-07-23

申请号：US12017961

申请日：2008-01-22

申请人： Yue-Song He ,  Len Mei

发明人： Yue-Song He ,  Len Mei

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/792 ,  H01L29/40117 ,  H01L29/42344

摘要： A memory device having a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a first trap-free-nitride layer formed on a channel region of a substrate, a second nitride layer formed on the first nitride layer, an oxide layer formed on the second nitride layer, a control gate formed on the high-K oxide layer, and a poly spacer as the select gate formed adjacent to the control gate.

摘要翻译： 具有与单元堆叠相邻形成的单元堆叠和选择栅极的存储器件。 电池堆包括形成在衬底的沟道区上的第一无陷波氮化物层，形成在第一氮化物层上的第二氮化物层，形成在第二氮化物层上的氧化物层， K氧化物层和作为选择栅极的多隔板作为与控制栅极相邻形成。

公开(公告)号：US07079424B1

公开(公告)日：2006-07-18

申请号：US10945914

申请日：2004-09-22

申请人： Sungchul Lee ,  Sheunghee Park ,  Yue-Song He ,  Ming Sang Kwan

发明人： Sungchul Lee ,  Sheunghee Park ,  Yue-Song He ,  Ming Sang Kwan

IPC分类号： G11C11/34

CPC分类号： G11C16/107 ,  G11C16/16 ,  G11C16/3468

摘要： A method is provided for erasing a memory cell having a substrate, a control gate, a floating gate, a source region and a drain region. The method includes pre-programming the memory cell to raise a threshold voltage of the memory cell to a first predetermined level, wherein pre-programming the memory cell does not include a verification process for ensuring that the threshold voltage of the memory cell has been raised to the first predetermined level. The memory cell may be erased to lower the threshold voltage of the memory cell to a second predetermined level.

摘要翻译： 提供一种用于擦除具有衬底，控制栅极，浮置栅极，源极区域和漏极区域的存储器单元的方法。 该方法包括对存储器单元预编程以将存储器单元的阈值电压升高到第一预定电平，其中预编程存储器单元不包括用于确保存储器单元的阈值电压已被提高的验证过程 到第一预定水平。 可以擦除存储器单元以将存储器单元的阈值电压降低到第二预定电平。

公开(公告)号：US06898124B1

公开(公告)日：2005-05-24

申请号：US10678446

申请日：2003-10-03

申请人： Zhigang Wang ,  Nian Yang ,  Yue-Song He

发明人： Zhigang Wang ,  Nian Yang ,  Yue-Song He

IPC分类号： G11C11/56 ,  G11C16/06 ,  G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： An exemplary sensing circuit comprises a first transistor connected to a first node, where a target memory cell has a drain capable of being connected to the first node through a selection circuit during a read operation involving the target memory cell. The sensing circuit further comprises a decouple circuit which is connected to the first transistor. The decouple circuit includes a second transistor having a gate coupled to a gate of the first transistor. The decouple circuit further has a decouple coefficient (N) greater than 1. The drain of the second transistor is connected at a second node to a reference voltage through a bias resistor. With the arrangement, the drain of the second transistor generates a sense amp input voltage at the second node such that the sense amp input voltage is decoupled from the first node.

摘要翻译： 示例性感测电路包括连接到第一节点的第一晶体管，其中目标存储器单元具有能够在涉及目标存储器单元的读取操作期间通过选择电路连接到第一节点的漏极。 感测电路还包括连接到第一晶体管的去耦电路。 解耦电路包括具有耦合到第一晶体管的栅极的栅极的第二晶体管。 去耦电路还具有大于1的去耦系数（N）。第二晶体管的漏极通过偏置电阻器在第二节点连接到参考电压。 利用该布置，第二晶体管的漏极在第二节点处产生感测放大器输入电压，使得感测放大器输入电压与第一节点分离。

公开(公告)号：US06833297B1

公开(公告)日：2004-12-21

申请号：US10265001

申请日：2002-10-04

申请人： Richard M. Fastow ,  Yue-Song He ,  Nga-Ching Wong

发明人： Richard M. Fastow ,  Yue-Song He ,  Nga-Ching Wong

IPC分类号： H01L218234

CPC分类号： H01L29/66825 ,  H01L29/7883

摘要： The present invention is a method for fabricating a memory device. In one embodiment, a first impurity concentration is deposited in a channel region of a memory device. A second impurity concentration, which overlies the first impurity concentration, is then created in the channel region. Finally, a memory array is fabricated upon the channel region. The memory array overlies the first impurity concentration and the second impurity concentration.

摘要翻译： 本发明是一种用于制造存储器件的方法。 在一个实施例中，第一杂质浓度沉积在存储器件的沟道区中。 然后在通道区域中产生第二杂质浓度，其覆盖第一杂质浓度。 最后，在通道区域上制造存储器阵列。 存储器阵列覆盖第一杂质浓度和第二杂质浓度。

公开(公告)号：US6143608A

公开(公告)日：2000-11-07

申请号：US283308

申请日：1999-03-31

申请人： Yue-Song He ,  Masaaki Higashitani ,  Hao Fang ,  Narbeh Derhacobian ,  Bill Cox ,  Kent Chang ,  Kelwin Ko ,  Maria Chow-Chan

发明人： Yue-Song He ,  Masaaki Higashitani ,  Hao Fang ,  Narbeh Derhacobian ,  Bill Cox ,  Kent Chang ,  Kelwin Ko ,  Maria Chow-Chan

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.

摘要翻译： 本发明描述了在半导体芯片的周边区域中制造栅极氧化物区域的方法，其中栅极氧化物区域具有改善的电性能。 所述方法包括在半导体芯片的周边上沉积阻挡层，以防止在半导体芯片的芯区域中的氮化步骤期间将杂质氮原子引入周围。 通过防止周围的栅极区域的污染，如此产生的栅极氧化物区域具有增加的击穿电压和增加的可靠性。 本发明描述了用于蚀刻用于保护周边免受隧道氧化物氮化的阻挡层的方法。 用本发明的方法制造的半导体器件具有更长的预期寿命，并且可以以较高的器件密度制造。

公开(公告)号：US08896048B1

公开(公告)日：2014-11-25

申请号：US10861581

申请日：2004-06-04

申请人： Richard Fastow ,  Zhigang Wang ,  Yue-Song He ,  Kazuhiro Mizutani ,  Pavel Fastenko

发明人： Richard Fastow ,  Zhigang Wang ,  Yue-Song He ,  Kazuhiro Mizutani ,  Pavel Fastenko

IPC分类号： H01L29/76

CPC分类号： H01L29/66659 ,  H01L29/66825 ,  H01L29/7881

摘要： The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.

摘要翻译： 本发明提供一种制造用于减少短沟道效应的金属氧化物半导体场效应晶体管（MOSFET）的装置和方法。 MOSFET包括半导体衬底，形成在半导体衬底上方的栅极堆叠，形成在栅极堆叠的漏极侧的漏极侧壁间隔物，形成在栅极堆叠的源极侧的源极侧壁隔离物，以及源极和漏极 地区。 源极区域形成在源极侧的半导体衬底中，并且通过源极侧壁间隔物对齐以在源极区域和漏极区域之间延伸有效沟道长度。 漏极区域形成在半导体衬底的漏极侧，并且通过漏极侧壁间隔物排列以进一步延长有效沟道长度。