利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

37 条记录 (耗时 0.02 秒)

    Multi-bank dynamic random access memory devices having all bank precharge capability
    2.
    发明授权
    Multi-bank dynamic random access memory devices having all bank precharge capability 有权
    具有全部预充电能力的多组动态随机存取存储器件

    公开(公告)号：US06343036B1

    公开(公告)日：2002-01-29

    申请号：US09157271

    申请日：1998-09-18

    申请人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    发明人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC分类号： G11C700

    CPC分类号： G11C7/1018 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

    摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    摘要翻译： 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于 灭活信号在预充电循环中工作。

    Method for updating a ROM BIOS
    3.
    发明授权
    Method for updating a ROM BIOS 失效
    更新ROM BIOS的方法

    公开(公告)号：US5964873A

    公开(公告)日：1999-10-12

    申请号：US12487

    申请日：1998-01-23

    申请人： Yun-Ho Choi

    发明人： Yun-Ho Choi

    IPC分类号： G06F9/06 ,  G06F9/24 ,  G06F9/445

    CPC分类号： G06F8/65

    摘要： A method for updating a ROM BIOS includes the following steps: a step for reading an image data of a ROM BIOS which is to be updated; a step for reading a ROM BIOS image data from a ROM BIOS; a step for reading a new ROM BIOS image data from an auxiliary memory; a step for reading a new user information; a step for converting the new user information into an image data; a step for updating the new ROM BIOS image data and user information in the ROM BIOS. Since the user updates a ROM BIOS image data for oneself, the user information displayed during a POST operation can be displayed in the user's characteristic message. Therefore, the user can recognize one's computer through unique characteristics that are displayed on a monitor and easily identify one's computer among many different computers.

    摘要翻译： 一种用于更新ROM BIOS的方法包括以下步骤：读取要更新的ROM BIOS的图像数据的步骤; 从ROM BIOS读取R​​OM BIOS图像数据的步骤; 从辅助存储器读取新的ROM BIOS图像数据的步骤; 阅读新用户信息的步骤; 将新用户信息转换为图像数据的步骤; 在ROM BIOS中更新新的ROM BIOS图像数据和用户信息的步骤。 由于用户更新自己的ROM BIOS图像数据，所以在POST操作期间显示的用户信息可以显示在用户的特征消息中。 因此，用户可以通过显示在显示器上的独特特征来识别自己的计算机，并且可以在许多不同的计算机之间轻松识别自己的计算机。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5610869A

    公开(公告)日：1997-03-11

    申请号：US511815

    申请日：1995-08-07

    申请人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    发明人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    IPC分类号： G11C5/14 ,  H02M3/07 ,  G11C13/00

    CPC分类号： H02M3/07 ,  G11C5/145

    摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

    摘要翻译： 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

    Burn-in circuit and burn-in test method
    5.
    发明授权
    Burn-in circuit and burn-in test method 失效
    老化电路和老化测试方法

    公开(公告)号：US5467356A

    公开(公告)日：1995-11-14

    申请号：US101243

    申请日：1993-08-02

    申请人： Yun-Ho Choi

    发明人： Yun-Ho Choi

    IPC分类号： G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/50 ,  G11C29/56

    CPC分类号： G11C29/50 ,  G11C11/401

    摘要： A burn-in enable circuit and burn-in test method of a semiconductor memory device are disclosed. A high voltage exceeding the external power voltage by a predetermined amount is applied to at least one of a plurality of pins normally used with a connected semiconductor memory chip to initiate a burn-in test mode. The burn-in test enable circuit senses this high voltage and causes the reset operation of word lines in the chip to become disabled. This allows for a high stress voltage to be applied to all access transistors in the chip simultaneously during a burn-in test for substantially the same amount of time. Therefore, burn-in time is substantially reduced and a reliable burn-in test is obtained.

    摘要翻译： 公开了一种半导体存储器件的老化实现电路和老化测试方法。 将超过外部电源电压的高电压施加到通常与连接的半导体存储器芯片一起使用的多个引脚中的至少一个以启动老化测试模式。 老化测试使能电路感测到这个高电压，并导致芯片中字线的复位操作变为禁止。 这允许在老化测试期间同时施加高应力电压到芯片中的所有存取晶体管，同时大致相同的时间量。 因此，大大降低了老化时间并获得可靠的老化测试。

    RF amplifier
    6.
    发明授权
    RF amplifier 失效
    射频放大器

    公开(公告)号：US07728672B2

    公开(公告)日：2010-06-01

    申请号：US12118562

    申请日：2008-05-09

    申请人： Yun-Ho Choi ,  Young-Ho Kim ,  Seok-Bong Hyun

    发明人： Yun-Ho Choi ,  Young-Ho Kim ,  Seok-Bong Hyun

    IPC分类号： H03F3/04

    CPC分类号： H03F3/189

    摘要： Provided is a radio frequency (RF) amplifier. The RF amplifier includes an amplification circuit amplifying an RF signal, a bias voltage generation circuit supplying a bias voltage of the amplification circuit, and a first bias resistor connected between the amplification circuit ad the bias voltage generation circuit, and having a predetermined resistance allowing the bias voltage to be affected by the RF signal.

    摘要翻译： 提供射频（RF）放大器。 RF放大器包括放大RF信号的放大电路，提供放大电路的偏置电压的偏置电压产生电路和连接在放大电路和偏置电压产生电路之间的第一偏置电阻，并且具有允许 偏置电压受RF信号的影响。

    Structure for preventing gap formation and plasma processing equipment having the same
    7.
    发明授权
    Structure for preventing gap formation and plasma processing equipment having the same 失效
    用于防止间隙形成的结构和具有其的等离子体处理设备

    公开(公告)号：US07727354B2

    公开(公告)日：2010-06-01

    申请号：US11971568

    申请日：2008-01-09

    申请人： Eui-Jin Park ,  Yun-Ho Choi ,  In-Young Park ,  Hwan-Il Jeong ,  Sung-Sok Choi

    发明人： Eui-Jin Park ,  Yun-Ho Choi ,  In-Young Park ,  Hwan-Il Jeong ,  Sung-Sok Choi

    IPC分类号： C23F1/00 ,  H01L21/306 ,  C23C16/00

    CPC分类号： H01L21/67126 ,  H01J37/32495 ,  H01L21/68735

    摘要： Plasma processing equipment having a structure for preventing gap formation includes: a chamber inside which a plasma environment is formed; an upper electrode positioned at a upper position of the chamber; an electrostatic chuck positioned at a lower position of the electrostatic chuck, having a lower electrode and holding a wafer on a top surface thereof; a ring positioned at an outer side of the electrostatic chuck; and a gap prevention unit for isolating from the outside a space between the electrostatic chuck and the ring.

    摘要翻译： 具有防止间隙形成的结构的等离子体处理设备包括：形成等离子体环境的室; 位于所述室的上部位置的上部电极; 位于所述静电卡盘的下部位置的静电卡盘，具有下部电极并且在其顶面保持晶片; 位于所述静电卡盘的外侧的环; 以及间隙防止单元，用于从外部隔离静电卡盘和环之间的空间。

    STRUCTURE FOR PREVENTING GAP FORMATION AND PLASMA PROCESSING EQUIPMENT HAVING THE SAME
    8.
    发明申请
    STRUCTURE FOR PREVENTING GAP FORMATION AND PLASMA PROCESSING EQUIPMENT HAVING THE SAME 失效
    用于防止GAP形成和等离子体处理设备的结构

    公开(公告)号：US20090044751A1

    公开(公告)日：2009-02-19

    申请号：US11971568

    申请日：2008-01-09

    申请人： Eui-Jin Park ,  Yun-Ho Choi ,  In-Young Park ,  Hwan-Il Jeong ,  Sung-Sok Choi

    发明人： Eui-Jin Park ,  Yun-Ho Choi ,  In-Young Park ,  Hwan-Il Jeong ,  Sung-Sok Choi

    IPC分类号： C23C16/54

    CPC分类号： H01L21/67126 ,  H01J37/32495 ,  H01L21/68735

    摘要： Plasma processing equipment having a structure for preventing gap formation includes: a chamber inside which a plasma environment is formed; an upper electrode positioned at a upper position of the chamber; an electrostatic chuck positioned at a lower position of the electrostatic chuck, having a lower electrode and holding a wafer on a top surface thereof; a ring positioned at an outer side of the electrostatic chuck; and a gap prevention unit for isolating from the outside a space between the electrostatic chuck and the ring.

    摘要翻译： 具有防止间隙形成的结构的等离子体处理设备包括：形成等离子体环境的室; 位于所述室的上部位置的上部电极; 位于所述静电卡盘的下部位置的静电卡盘，具有下部电极并且在其顶面保持晶片; 位于所述静电卡盘的外侧的环; 以及间隙防止单元，用于从外部隔离静电卡盘和环之间的空间。

    Semiconductor memory having a plurality of I/O buses
    9.
    发明授权
    Semiconductor memory having a plurality of I/O buses 失效
    具有多个I / O总线的半导体存储器

    公开(公告)号：US5590086A

    公开(公告)日：1996-12-31

    申请号：US580481

    申请日：1995-12-29

    申请人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    发明人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    摘要翻译： 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5446697A

    公开(公告)日：1995-08-29

    申请号：US068547

    申请日：1993-05-28

    申请人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    发明人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    IPC分类号： G11C5/14 ,  H02M3/07 ,  G11C13/00

    CPC分类号： H02M3/07 ,  G11C5/145

    摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

    摘要翻译： 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。