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公开(公告)号：US20070108572A1
公开(公告)日：2007-05-17
申请号：US11410986
申请日：2006-04-26
申请人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuah Cheng
发明人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuah Cheng
IPC分类号： H01L21/00
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L23/562 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K3/4644 , H05K2201/068 , H05K2201/09509 , H05K2201/09563 , H05K2201/09781 , H05K2201/09909 , H01L2924/00
摘要： A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
摘要翻译： 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。
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公开(公告)号：US07545039B2
公开(公告)日：2009-06-09
申请号：US11410986
申请日：2006-04-26
申请人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuah Cheng
发明人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuah Cheng
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L23/562 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K3/4644 , H05K2201/068 , H05K2201/09509 , H05K2201/09563 , H05K2201/09781 , H05K2201/09909 , H01L2924/00
摘要： A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
摘要翻译： 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。
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公开(公告)号：US07754599B2
公开(公告)日：2010-07-13
申请号：US12379223
申请日：2009-02-17
申请人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuan Cheng
发明人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuan Cheng
IPC分类号： H01L21/44
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L23/562 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K3/4644 , H05K2201/068 , H05K2201/09509 , H05K2201/09563 , H05K2201/09781 , H05K2201/09909 , H01L2924/00
摘要： A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
摘要翻译： 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。
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公开(公告)号：US20090156001A1
公开(公告)日：2009-06-18
申请号：US12379223
申请日：2009-02-17
申请人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuan Cheng
发明人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuan Cheng
IPC分类号： H01L21/768
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L23/562 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K3/4644 , H05K2201/068 , H05K2201/09509 , H05K2201/09563 , H05K2201/09781 , H05K2201/09909 , H01L2924/00
摘要： A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
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5.发明授权公开(公告)号：US08026603B2
公开(公告)日：2011-09-27
申请号：US11408072
申请日：2006-04-21
申请人： Yung-Yu Hsu , Chih-Yuan Cheng , Shyi-Ching Liau , Min-Lin Lee , Ra-Min Tain , Rong-Chang Feng
发明人： Yung-Yu Hsu , Chih-Yuan Cheng , Shyi-Ching Liau , Min-Lin Lee , Ra-Min Tain , Rong-Chang Feng
IPC分类号： H01L23/52
CPC分类号： H01L24/12 , H01L23/49811 , H01L24/11 , H01L24/16 , H01L24/90 , H01L2224/1147 , H01L2224/11902 , H01L2224/13099 , H01L2224/1411 , H01L2224/16105 , H01L2224/16106 , H01L2224/16237 , H01L2224/81193 , H01L2224/81194 , H01L2224/81385 , H01L2224/81899 , H01L2924/01006 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H05K3/326 , H05K2201/0373 , H05K2201/209 , H01L2924/00
摘要： An interconnect structure of an integrated circuit and manufacturing method therefore are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.
摘要翻译： 因此，提供了与柔性包装的互连结构相关的集成电路和制造方法的互连结构。 互连结构包括第一和第二导电焊盘。 多个微小且导电的第一支柱分别形成在第一和第二垫上。 当第一和第二支柱具有不同的密度和厚度时，当支柱互相连接时，可以产生接触强度，使得支柱紧密连接。 此外，互连结构也可以用于与由导电材料制成的纤维连接。 此外，支柱的密度越高，接触强度越强。 并且，电子基板和有源或无源电子元件可以卡在每个垫的另一侧上。 因此，互连结构可以保持柔性并且具有高可靠性，而不会被任何热固性聚合物增强。
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6.发明申请公开(公告)号：US20070128845A1
公开(公告)日：2007-06-07
申请号：US11408072
申请日：2006-04-21
申请人： Yung-Yu Hsu , Chih-Yuan Chen , Shyi-Ching Liau , Min-Lin Lee , Ra-Min Tain , Rong-Chang Feng
发明人： Yung-Yu Hsu , Chih-Yuan Chen , Shyi-Ching Liau , Min-Lin Lee , Ra-Min Tain , Rong-Chang Feng
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L24/12 , H01L23/49811 , H01L24/11 , H01L24/16 , H01L24/90 , H01L2224/1147 , H01L2224/11902 , H01L2224/13099 , H01L2224/1411 , H01L2224/16105 , H01L2224/16106 , H01L2224/16237 , H01L2224/81193 , H01L2224/81194 , H01L2224/81385 , H01L2224/81899 , H01L2924/01006 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H05K3/326 , H05K2201/0373 , H05K2201/209 , H01L2924/00
摘要： An interconnect structure of an integrated circuit and manufacturing method therefor are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.
摘要翻译： 提供了一种集成电路的互连结构及其制造方法，涉及柔性封装的互连结构。 互连结构包括第一和第二导电焊盘。 多个微小且导电的第一支柱分别形成在第一和第二垫上。 当第一和第二支柱具有不同的密度和厚度时，当支柱互相连接时，可以产生接触强度，使得支柱紧密连接。 此外，互连结构也可以用于与由导电材料制成的纤维连接。 此外，支柱的密度越高，接触强度越强。 并且，电子基板和有源或无源电子元件可以卡在每个垫的另一侧上。 因此，互连结构可以保持柔性并且具有高可靠性，而不会被任何热固性聚合物增强。
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7.发明授权Interconnect structure with stress buffering ability and the manufacturing method thereof 有权具有应力缓冲能力的互连结构及其制造方法公开(公告)号：US08123965B2
公开(公告)日：2012-02-28
申请号：US12170272
申请日：2008-07-09
申请人： Yung-Yu Hsu , Shyi-Ching Liau , Ra-Min Tain , Jr-Yuan Jeng
发明人： Yung-Yu Hsu , Shyi-Ching Liau , Ra-Min Tain , Jr-Yuan Jeng
CPC分类号： H01L21/4853 , H01L23/49811 , H01L24/11 , H01L24/12 , H01L24/742 , H01L2224/05001 , H01L2224/05022 , H01L2224/05571 , H01L2224/111 , H01L2224/13076 , H01L2224/13078 , H01L2224/13099 , H01L2224/13147 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/368 , H05K2201/10242 , H05K2201/10265 , H01L2224/05599 , H01L2224/05099
摘要： An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.
摘要翻译： 公开了具有应力缓冲能力的互连结构，其包括：第一表面，连接到由基板和电子器件组成的组中选择的器件; 第二表面，连接到从由所述基板和所述电子装置组成的组中选择的装置; 支撑部分，夹持在第一和第二表面之间并互相连接，同时使得支撑部分的两个端部的区域相对于第一和第二表面的面积小; 以及缓冲器，其布置成围绕所述支撑部分以吸收和缓冲应力。
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8.发明授权公开(公告)号：US07586187B2
公开(公告)日：2009-09-08
申请号：US11473271
申请日：2006-06-23
申请人： Yung-Yu Hsu , Shyi-Ching Liau , Ra-Min Tain , Jr-Yuan Jeng
发明人： Yung-Yu Hsu , Shyi-Ching Liau , Ra-Min Tain , Jr-Yuan Jeng
IPC分类号： H01L23/04
CPC分类号： H01L21/4853 , H01L23/49811 , H01L24/11 , H01L24/12 , H01L24/742 , H01L2224/05001 , H01L2224/05022 , H01L2224/05571 , H01L2224/111 , H01L2224/13076 , H01L2224/13078 , H01L2224/13099 , H01L2224/13147 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/368 , H05K2201/10242 , H05K2201/10265 , H01L2224/05599 , H01L2224/05099
摘要： An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.
摘要翻译： 公开了具有应力缓冲能力的互连结构，其包括：第一表面，连接到由基板和电子器件组成的组中选择的器件; 第二表面，连接到从由所述基板和所述电子装置组成的组中选择的装置; 支撑部分，夹持在第一和第二表面之间并互相连接，同时使得支撑部分的两个端部的区域相对于第一和第二表面的面积小; 以及缓冲器，其布置成围绕所述支撑部分以吸收和缓冲应力。
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9.发明申请Interconnect structure with stress buffering ability and the manufacturing method thereof 失效具有应力缓冲能力的互连结构及其制造方法公开(公告)号：US20070228549A1
公开(公告)日：2007-10-04
申请号：US11473271
申请日：2006-06-23
申请人： Yung-Yu Hsu , Shyi- Liau , Ra-Min Tain , Jr-Yuan Jeng
发明人： Yung-Yu Hsu , Shyi- Liau , Ra-Min Tain , Jr-Yuan Jeng
IPC分类号： H01L23/04
CPC分类号： H01L21/4853 , H01L23/49811 , H01L24/11 , H01L24/12 , H01L24/742 , H01L2224/05001 , H01L2224/05022 , H01L2224/05571 , H01L2224/111 , H01L2224/13076 , H01L2224/13078 , H01L2224/13099 , H01L2224/13147 , H01L2924/00014 , H01L2924/01006 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H05K3/368 , H05K2201/10242 , H05K2201/10265 , H01L2224/05599 , H01L2224/05099
摘要： An interconnect structure with stress buffering ability is disclosed, which comprises: a first surface, connected to a device selected form the group consisting of a substrate and an electronic device; a second surface, connected to a device selected form the group consisting of the substrate and the electronic device; a supporting part, sandwiched between and interconnecting the first and the second surfaces while enabling the areas of the two ends of the supporting part to be small than those of the first and the second surfaces in respective; and a buffer, arranged surrounding the supporting part for absorbing and buffering stresses.
摘要翻译： 公开了具有应力缓冲能力的互连结构，其包括：第一表面，连接到由基板和电子器件组成的组中选择的器件; 第二表面，连接到从由所述基板和所述电子装置组成的组中选择的装置; 支撑部分，夹持在第一和第二表面之间并互相连接，同时使得支撑部分的两个端部的区域相对于第一和第二表面的面积小; 以及缓冲器，其布置成围绕所述支撑部分以吸收和缓冲应力。
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公开(公告)号：US20130245388A1
公开(公告)日：2013-09-19
申请号：US13603290
申请日：2012-09-04
申请人： Conor Rafferty , Jeffrey D. Carbeck , Alexander Dickson , Kevin Dowling , Yung-Yu Hsu , Isaiah Kacyvenski , Benjamin Schlatka , Henry Wei
发明人： Conor Rafferty , Jeffrey D. Carbeck , Alexander Dickson , Kevin Dowling , Yung-Yu Hsu , Isaiah Kacyvenski , Benjamin Schlatka , Henry Wei
CPC分类号： A61B5/0537 , A61B5/0002 , A61B5/0024 , A61B5/01 , A61B5/024 , A61B5/0245 , A61B5/04 , A61B5/04012 , A61B5/0402 , A61B5/0476 , A61B5/0488 , A61B5/0531 , A61B5/0533 , A61B5/112 , A61B5/4266 , A61B5/441 , A61B5/442 , A61B5/443 , A61B5/6831 , A61B5/6832 , A61B5/6833 , A61B5/7282 , A61B8/4416 , A61B2562/16
摘要： Apparatus are provided for monitoring a condition of a tissue based on a measurement of an electrical property of the tissue. In an example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least two conductive structures, each having a non-linear configuration, where the at least two conductive structures are disposed substantially parallel to each other. In another example, the electrical property of the tissue is performed using an apparatus disposed above the tissue, where the apparatus includes at least one inductor structure.
摘要翻译： 提供了用于基于组织的电性质的测量来监测组织的状况的装置。 在一个示例中，使用设置在组织上方的装置来执行组织的电性能，其中该装置包括至少两个导电结构，每个导电结构具有非线性构造，其中至少两个导电结构被设置为基本上平行于 彼此。 在另一示例中，使用设置在组织上方的装置来执行组织的电特性，其中该装置包括至少一个电感器结构。
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