公开(公告)号：US07732928B2

公开(公告)日：2010-06-08

申请号：US11516944

申请日：2006-09-06

Applicant: Shyh-Ming Chang ,  Ji-Cheng Lin ,  Shou-Lung Chen

Inventor： Shyh-Ming Chang ,  Ji-Cheng Lin ,  Shou-Lung Chen

IPC: H01L23/02 ,  H01L27/115

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311

Abstract: A structure for protecting electronic package contacts is provided. The structure includes at least an electronic contact mounted on a chip, a dielectric layer, a conductor trace line and a protective layer. The protective layer is used to prevent stresses from being gathered within electronic contacts on the chip through surroundingly covering the conductor trace line.

Abstract translation: 提供了一种用于保护电子封装触点的结构。 该结构至少包括安装在芯片，电介质层，导体迹线和保护层上的电子触点。 保护层用于通过周围覆盖导体迹线来防止应力集中在芯片上的电子触点内。

公开(公告)号：US07378746B2

公开(公告)日：2008-05-27

申请号：US11308180

申请日：2006-03-10

Applicant: Ji-Cheng Lin ,  Yao-Sheng Lin ,  Shyh-Ming Chang ,  Su-Tsai Lu ,  Hsien-Chie Cheng ,  Tai-Hong Chen

Inventor： Ji-Cheng Lin ,  Yao-Sheng Lin ,  Shyh-Ming Chang ,  Su-Tsai Lu ,  Hsien-Chie Cheng ,  Tai-Hong Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/10 ,  H01L23/49811 ,  H01L24/13 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A composite bump suitable for disposing on a substrate pad is provided. The composite bump includes a compliant body and an outer conductive layer. The coefficient of thermal expansion (CTE) of the compliant body is between 5 ppm/° C. and 200 ppm/° C. The outer conductive layer covers the compliant body and is electrically connected to the pad. The compliant body can provide a stress buffering effect for a bonding operation. Furthermore, by setting of the CTE of the compliant body within a preferable range, damages caused by thermal stress are reduced while the bonding effect is enhanced.

Abstract translation: 提供了适合于设置在基板焊盘上的复合凸块。 复合凸块包括柔性本体和外导电层。 柔性体的热膨胀系数（CTE）在5ppm /℃和200ppm /℃之间。外部导电层覆盖柔性体并与衬垫电连接。 柔性体可以为粘接操作提供应力缓冲效果。 此外，通过将柔性体的CTE设定在优选范围内，由于热应力引起的损伤降低，同时结合效果增强。

公开(公告)号：US06541834B1

公开(公告)日：2003-04-01

申请号：US09975125

申请日：2001-10-09

Applicant: Jin-shown Shie ,  Ji-cheng Lin ,  Chun-te Lin ,  Chih-tang Peng ,  Shih-han Yu ,  Kuo-ning Chiang

Inventor： Jin-shown Shie ,  Ji-cheng Lin ,  Chun-te Lin ,  Chih-tang Peng ,  Shih-han Yu ,  Kuo-ning Chiang

IPC: H01L2982

CPC classification number: B81C1/00182 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/014 ,  B81C2201/016 ,  G01L9/0054

Abstract: The invention is a silicon pressure micro-sensing device and the fabrication process thereof. The silicon pressure micro-sensing device includes a pressure chamber, and is constituted of a P-type substrate with a taper chamber and an N-type epitaxial layer thereon. On the N-type epitaxial layer are a plurality of piezo-resistance sensing units which sense deformation caused by pressure. The fabrication pressure of the silicon pressure micro-sensing device includes a step of first making a plurality of holes on the N-type epitaxial layer to reach the P-type substrate beneath. Then, by an anisotropic etching stop technique, in which etchant pass through the holes, a taper chamber is formed in the P-type substrate. Finally, an insulating material is applied to seal the holes, thus attaining the silicon pressure micro-sensing device that is able to sense pressure differences between two ends thereof.

Abstract translation: 本发明是一种硅压力微型感测装置及其制造方法。 硅压力微型感测装置包括压力室，由具有锥形室的P型衬底和其上的N型外延层构成。 在N型外延层上是感测由压力引起的变形的多个压电感测单元。 硅压力微型感测装置的制造压力包括首先在N型外延层上制造多个孔以到达下面的P型衬底的步骤。 然后，通过各向异性蚀刻停止技术，其中蚀刻剂穿过孔，在P型衬底中形成锥形室。 最后，施加绝缘材料以密封孔，从而获得能够感测其两端之间的压力差的硅压力微检测装置。

公开(公告)号：US20070108572A1

公开(公告)日：2007-05-17

申请号：US11410986

申请日：2006-04-26

Applicant: Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuah Cheng

Inventor： Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuah Cheng

IPC: H01L21/00

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2201/09909 ,  H01L2924/00

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Abstract translation: 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。

公开(公告)号：US07754599B2

公开(公告)日：2010-07-13

申请号：US12379223

申请日：2009-02-17

Applicant: Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuan Cheng

Inventor： Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-Cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuan Cheng

IPC: H01L21/44

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2201/09909 ,  H01L2924/00

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Abstract translation: 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。

公开(公告)号：US07691676B1

公开(公告)日：2010-04-06

申请号：US12271435

申请日：2008-11-14

Applicant: Wen-Jeng Fan ,  Li-Chih Fang ,  Ji-Cheng Lin

Inventor： Wen-Jeng Fan ,  Li-Chih Fang ,  Ji-Cheng Lin

IPC: H01L21/00

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A mold array process (MAP) for manufacturing a plurality of semiconductor packages is revealed. Firstly, a substrate strip including a plurality of substrate units arranged in an array within a molding area is provided. A plurality of chips are disposed on the substrate units. An encapsulant by molding is formed on the molding area of the substrate strip to continuously encapsulate the chips. During the molding process, an adjustable top mold is implemented where a cavity width between two opposing sidewalls inside a top mold chest can be adjusted to make the mold flow speeds at the center and at the side rails of the molding area the same.

Abstract translation: 揭示了用于制造多个半导体封装的模具阵列工艺（MAP）。 首先，提供包括在成型区域内排列成阵列的多个基板单元的基板条。 多个芯片设置在基板单元上。 通过模制的密封剂形成在衬底条的成型区域上以连续地包封芯片。 在模制过程中，实现可调节的顶模，其中可以调节顶模箱内的两个相对的侧壁之间的空腔宽度，以使成型区域的中心和侧轨处的模具流速相同。

公开(公告)号：US07531900B2

公开(公告)日：2009-05-12

申请号：US11554597

申请日：2006-10-31

Applicant: Ji-Cheng Lin ,  Shyh-Ming Chang

Inventor： Ji-Cheng Lin ,  Shyh-Ming Chang

IPC: H01L23/48

CPC classification number: H01L24/12 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/2402 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A package structure with embedded electronic devices is provided. The package structure includes a substrate, a multi-layered circuit board, an adhesive film and at least an electronic device. The electronic device is disposed on the substrate. The electronic device is press-adhered to the multi-layered circuit board through the adhesive film and the composite bump thereon, so that the electronic device is embedded within the package structure and between the substrate and the circuit board. Due to the deformity of the composite bump, the electronic device is protected from being cracking in the pressing process.

Abstract translation: 提供了具有嵌入式电子设备的封装结构。 封装结构包括衬底，多层电路板，粘合膜和至少一个电子器件。 电子设备设置在基板上。 电子器件通过粘合剂膜及其上的复合凸块压接到多层电路板上，使得电子器件嵌入在封装结构内，衬底与电路板之间。 由于复合凸块的变形，电子器件在压制过程中被保护不会开裂。

公开(公告)号：US20070210429A1

公开(公告)日：2007-09-13

申请号：US11554597

申请日：2006-10-31

Applicant: Ji-Cheng Lin ,  Shyh-Ming Chang

Inventor： Ji-Cheng Lin ,  Shyh-Ming Chang

IPC: H01L23/02

CPC classification number: H01L24/12 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/2402 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A package structure with embedded electronic devices is provided. The package structure includes a substrate, a multi-layered circuit board, an adhesive film and at least an electronic device. The electronic device is disposed on the substrate. The electronic device is press-adhered to the multi-layered circuit board through the adhesive film and the composite bump thereon, so that the electronic device is embedded within the package structure and between the substrate and the circuit board. Due to the deformity of the composite bump, the electronic device is protected from being cracking in the pressing process.

Abstract translation: 提供了具有嵌入式电子设备的封装结构。 封装结构包括衬底，多层电路板，粘合膜和至少一个电子器件。 电子设备设置在基板上。 电子设备通过粘合剂膜及其上的复合凸块压接到多层电路板上，使得电子器件嵌入在封装结构内，衬底与电路板之间。 由于复合凸块的变形，电子器件在压制过程中被保护不会开裂。

公开(公告)号：US20070096279A1

公开(公告)日：2007-05-03

申请号：US11516944

申请日：2006-09-06

Applicant: Shyh-Ming Chang ,  Ji-Cheng Lin ,  Shou-Lung Chen

Inventor： Shyh-Ming Chang ,  Ji-Cheng Lin ,  Shou-Lung Chen

IPC: H01L23/02

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24227 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311

Abstract: A structure for protecting electronic package contacts and the method for manufacturing the same are provided. The protective layer is used to prevent stresses from being gathered within electronic contacts on the chip and the vias for rerouting so as to raise the reliability of the conductor trace line in the electronic package structure. The protecting layer is formed in the wafer-level manufacturing processes by coating, depositing, and printing. The method is suitable for all kinds of electronic package structures owing to its high compatibility.

Abstract translation: 提供了一种用于保护电子封装触点的结构及其制造方法。 保护层用于防止应力集中在芯片上的电子触点和用于重新布线的通孔中，以提高电子封装结构中的导体迹线的可靠性。 通过涂布，沉积和印刷在晶片级制造工艺中形成保护层。 该方法由于兼容性高，适用于各种电子封装结构。

公开(公告)号：US20090156001A1

公开(公告)日：2009-06-18

申请号：US12379223

申请日：2009-02-17

Applicant: Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuan Cheng

Inventor： Yung-Yu Hsu ,  Rong-Chang Feng ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Ji-cheng Lin ,  Shan-Pu Yu ,  Shou-Lung Chen ,  Chih-Yuan Cheng

IPC: H01L21/768

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2201/09909 ,  H01L2924/00

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.