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公开(公告)号：US07754599B2
公开(公告)日：2010-07-13
申请号：US12379223
申请日：2009-02-17
申请人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuan Cheng
发明人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuan Cheng
IPC分类号： H01L21/44
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L23/562 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K3/4644 , H05K2201/068 , H05K2201/09509 , H05K2201/09563 , H05K2201/09781 , H05K2201/09909 , H01L2924/00
摘要： A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
摘要翻译： 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。
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公开(公告)号：US20090156001A1
公开(公告)日：2009-06-18
申请号：US12379223
申请日：2009-02-17
申请人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuan Cheng
发明人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuan Cheng
IPC分类号： H01L21/768
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L23/562 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K3/4644 , H05K2201/068 , H05K2201/09509 , H05K2201/09563 , H05K2201/09781 , H05K2201/09909 , H01L2924/00
摘要： A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
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公开(公告)号：US20070108572A1
公开(公告)日：2007-05-17
申请号：US11410986
申请日：2006-04-26
申请人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuah Cheng
发明人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuah Cheng
IPC分类号： H01L21/00
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L23/562 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K3/4644 , H05K2201/068 , H05K2201/09509 , H05K2201/09563 , H05K2201/09781 , H05K2201/09909 , H01L2924/00
摘要： A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
摘要翻译： 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。
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公开(公告)号：US07545039B2
公开(公告)日：2009-06-09
申请号：US11410986
申请日：2006-04-26
申请人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuah Cheng
发明人： Yung-Yu Hsu , Rong-Chang Feng , Ra-Min Tain , Shyi-Ching Liau , Ji-Cheng Lin , Shan-Pu Yu , Shou-Lung Chen , Chih-Yuah Cheng
CPC分类号： H05K1/115 , H01L21/486 , H01L23/49827 , H01L23/562 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/211 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/3025 , H01L2924/351 , H05K1/0271 , H05K3/4644 , H05K2201/068 , H05K2201/09509 , H05K2201/09563 , H05K2201/09781 , H05K2201/09909 , H01L2924/00
摘要： A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.
摘要翻译： 提供一种用于减小通孔应力的结构及其制造方法。 使用栅格结构中的应力块与绝缘材料的主要部分直接接触，具有高的热膨胀系数，使厚度方向上的一个或多个导线或通孔被固定。 因此，由温度加载引起的剪切应力可以被应力块阻挡或吸收。
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公开(公告)号：US08587091B2
公开(公告)日：2013-11-19
申请号：US13533251
申请日：2012-06-26
申请人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
摘要翻译： 一种晶片级芯片封装方法，包括以下步骤：提供晶片; 将至少一个第一芯片附接到晶片; 在晶片上形成第一绝缘层; 形成穿过所述第一绝缘层的多个第一导电通孔，其中所述第一导电通孔的部分与所述第一芯片电连接; 在所述第一绝缘层的表面上形成导电图案层，其中所述导电图案层与所述第一导电通孔电连接; 形成穿过晶片的多个通孔; 在通孔中填充第二绝缘层; 以及在所述第二绝缘层中形成多个第二导电通孔，其中所述第二导电通孔与所述第一导电通孔电连接。
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公开(公告)号：US07411306B2
公开(公告)日：2008-08-12
申请号：US11194669
申请日：2005-08-02
申请人： Fang-Jun Leu , Shou-Lung Chen , Ching-Wen Hsiao , Shan-Pu Yu , Jyh-Rong Lin , I-Hsuan Peng , Jian-Shu Wu , Hui-Mei Wu , Chien-Wei Chieh
发明人： Fang-Jun Leu , Shou-Lung Chen , Ching-Wen Hsiao , Shan-Pu Yu , Jyh-Rong Lin , I-Hsuan Peng , Jian-Shu Wu , Hui-Mei Wu , Chien-Wei Chieh
CPC分类号： H01L31/0203 , H01L27/14618 , H01L2224/16225 , H01L2224/24226 , H01L2924/00011 , H01L2924/00014 , H01L2924/07811 , H01L2924/15321 , H01L2924/19105 , H01L2924/00 , H01L2224/0401
摘要： This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.
摘要翻译： 本发明涉及图像传感器模块的封装结构和方法。 该方法包括：提供具有第一图案化导电层的透明基板; 在所述透明基板上承载具有感光有源区域的图像传感器集成电路芯片和至少一个无源芯片，其中所述光敏有源区域面向所述透明基板; 在透明基板上形成绝缘堆积膜; 并且在绝缘堆积膜中形成多个导电通孔，其中导电通孔的端部与透明基板的无源芯片或第一图案化导电层连接，而导电通孔的另一端暴露在表面上 的绝缘堆积膜。 包装方法能够缩小图像传感器模块的结构，简化了处理步骤。
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公开(公告)号：US20060030070A1
公开(公告)日：2006-02-09
申请号：US11194669
申请日：2005-08-02
申请人： Fang-Jun Leu , Shou-Lung Chen , Ching-Wen Hsiao , Shan-Pu Yu , Jyh-Rong Lin , I-Hsuan Peng , Jian-Shu Wu , Hui-Mei Wu , Chien-Wei Chieh
发明人： Fang-Jun Leu , Shou-Lung Chen , Ching-Wen Hsiao , Shan-Pu Yu , Jyh-Rong Lin , I-Hsuan Peng , Jian-Shu Wu , Hui-Mei Wu , Chien-Wei Chieh
CPC分类号： H01L31/0203 , H01L27/14618 , H01L2224/16225 , H01L2224/24226 , H01L2924/00011 , H01L2924/00014 , H01L2924/07811 , H01L2924/15321 , H01L2924/19105 , H01L2924/00 , H01L2224/0401
摘要： This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.
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公开(公告)号：US20060022290A1
公开(公告)日：2006-02-02
申请号：US11222173
申请日：2005-09-08
申请人： Shou-Lung Chen , Fang-Jun Leu , Shan-Pu Yu
发明人： Shou-Lung Chen , Fang-Jun Leu , Shan-Pu Yu
IPC分类号： H01L21/00 , H01L31/0232
CPC分类号： H01L31/0203 , H01L23/15 , H01L24/24 , H01L24/82 , H01L27/14618 , H01L27/14625 , H01L27/14636 , H01L27/14683 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16225 , H01L2224/2402 , H01L2224/24226 , H01L2224/32145 , H01L2224/48091 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/1532 , H01L2924/16195 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An image sensor module includes a first substrate, a second substrate provided over the first substrate, an image sensor device for receiving an image signal flip-chip bonded to the second substrate, and a semiconductor device for processing the image signal from the image sensor device embedded in the first substrate.
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公开(公告)号：US20070197018A1
公开(公告)日：2007-08-23
申请号：US11785612
申请日：2007-04-19
申请人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
发明人： Shou-Lung Chen , Ching-Wen Hsiao , Yu-Hua Chen , Jeng-Dar Ko , Chih-Ming Tzeng , Jyh-Rong Lin , Shan-Pu Yu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5384 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L23/3128 , H01L23/34 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/73267 , H01L2224/82039 , H01L2224/94 , H01L2224/97 , H01L2225/06524 , H01L2225/06541 , H01L2225/06586 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01072 , H01L2924/01078 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/351 , H01L2224/83 , H01L2924/00 , H01L2224/82
摘要： This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
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公开(公告)号：US07091592B2
公开(公告)日：2006-08-15
申请号：US10780875
申请日：2004-02-19
申请人： Shou-Lung Chen , Fang-Jun Leu , I-Hsuan Peng , Shan-Pu Yu
发明人： Shou-Lung Chen , Fang-Jun Leu , I-Hsuan Peng , Shan-Pu Yu
CPC分类号： H01L25/0657 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/09701 , H01L2224/05599
摘要： A stacked package for electronic elements is provided, a plurality of stud bumps are formed on a substrate by means of a stud bump process to align with a plurality of vias of one provided electronic element. The stud bumps respectively pass through the vias and electrically connect the electronic element. Furthermore, additional electronic elements are stacked on the carrier according to a similar way to form a stacked electronic package.
摘要翻译： 提供了一种用于电子元件的堆叠封装件，通过柱形凸起工艺在基板上形成多个柱形突起，以与一个所提供的电子元件的多个通孔对准。 螺柱凸块分别穿过通孔并电连接电子元件。 此外，附加的电子元件根据类似的方式堆叠在载体上以形成堆叠的电子封装。
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