摘要:
One embodiment of the present invention provides a system that generates a pattern-clip-based hotspot database for performing automatic pattern-clip-based layout verification. During operation, the system receives a list of pattern clips which specify manufacturing hotspots to be avoided in a layout, wherein each pattern clip comprises a set of geometries in proximity to each other. Next, for each pattern clip, the system perturbs the pattern clip to determine a first range of variations for the constituent set of geometries wherein the perturbed pattern clip no longer causes a manufacturing hotspot. The system then extracts a set of correction guidance descriptions from the first range of variations for correcting the pattern clip. Subsequently, the system stores the pattern clip and the set of correction guidance descriptions in the pattern-clip-based hotspot database.
摘要:
One embodiment of the present invention provides a system that generates a pattern-clip-based hotspot database for performing automatic pattern-clip-based layout verification. During operation, the system receives a list of pattern clips which specify manufacturing hotspots to be avoided in a layout, wherein each pattern clip comprises a set of geometries in proximity to each other. Next, for each pattern clip, the system perturbs the pattern clip to determine a first range of variations for the constituent set of geometries wherein the perturbed pattern clip no longer causes a manufacturing hotspot. The system then extracts a set of correction guidance descriptions from the first range of variations for correcting the pattern clip. Subsequently, the system stores the pattern clip and the set of correction guidance descriptions in the pattern-clip-based hotspot database.
摘要:
One embodiment of the present invention provides a system that automatically processes manufacturing hotspot information. During operation, the system receives a pattern clip associated with a manufacturing hotspot in a layout, wherein the pattern clip comprises a set of polygons in proximity to the manufacturing hotspot's location. Next, the system determines if the pattern clip matches a known manufacturing hotspot configuration. If the pattern clip does not match a known manufacturing hotspot configuration, the system then performs a perturbation process on the pattern clip to determine a set of correction recommendations to eliminate the manufacturing hotspot. By performing the perturbation process, the system additionally determines ranges of perturbation to the set of polygons wherein the perturbed pattern clip does not eliminate the manufacturing hotspot. Subsequently, the system stores the set of correction recommendations and the ranges of perturbation into a manufacturing hotspot database.
摘要:
One embodiment of the present invention provides a system that automatically processes manufacturing hotspot information. During operation, the system receives a pattern clip associated with a manufacturing hotspot in a layout, wherein the pattern clip comprises a set of polygons in proximity to the manufacturing hotspot's location. Next, the system determines if the pattern clip matches a known manufacturing hotspot configuration. If the pattern clip does not match a known manufacturing hotspot configuration, the system then performs a perturbation process on the pattern clip to determine a set of correction recommendations to eliminate the manufacturing hotspot. By performing the perturbation process, the system additionally determines ranges of perturbation to the set of polygons wherein the perturbed pattern clip does not eliminate the manufacturing hotspot. Subsequently, the system stores the set of correction recommendations and the ranges of perturbation into a manufacturing hotspot database.
摘要:
One embodiment of the present invention provides a system that verifies an integrated circuit (IC) chip layout. During operation, the system receives a layout of an IC chip after the layout has gone through a place-and-route operation. Next, the system performs a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot. Next, for each detected lithography hotspot, the system compares the associated local routing pattern against a hotspot database to determine if the local routing pattern matches an entry in the hotspot database, which stores a set of known hotspot configurations. If so, the system corrects the lithography hotspot using correction guidance information associated with the hotspot configuration stored in the hotspot database. Otherwise, the system corrects the lithography hotspot by performing a local rip-up and reroute on the local routing pattern, iteratively, until achieving convergence or given number of iterations.
摘要:
One embodiment of the present invention provides a system that verifies an integrated circuit (IC) chip layout. During operation, the system receives a layout of an IC chip after the layout has gone through a place-and-route operation. Next, the system performs a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot. Next, for each detected lithography hotspot, the system compares the associated local routing pattern against a hotspot database to determine if the local routing pattern matches an entry in the hotspot database, which stores a set of known hotspot configurations. If so, the system corrects the lithography hotspot using correction guidance information associated with the hotspot configuration stored in the hotspot database. Otherwise, the system corrects the lithography hotspot by performing a local rip-up and reroute on the local routing pattern, iteratively, until achieving convergence or given number of iterations.
摘要:
A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed.
摘要:
A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed.
摘要:
Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.
摘要:
A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements. The system then computes environments for cell placements based on the skeleton. Next, the system generates templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement. The system then generates the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.