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    Integrated circuits having single state memory reference cells and methods for operating the same
    4.
    发明授权
    Integrated circuits having single state memory reference cells and methods for operating the same 有权

    公开(公告)号：US10460782B1

    公开(公告)日：2019-10-29

    申请号：US16055952

    申请日：2018-08-06

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Yentsai Huang

    IPC: G11C11/00 ,  G11C11/16 ,  G06F11/07 ,  G11C13/00

    Abstract: Integrated circuits including memory cells and methods for operating memory cells are provided. In an embodiment, a method is provided for operating a memory including a plurality of operational memory cells. The method includes providing a word line voltage on a selected word line corresponding to a selected operational memory cell of the plurality of operational memory cells and to a corresponding reference memory cell. The method includes applying an operational bias current on an operational bit line to the selected operational memory cell. Also, the method includes scanning a reference bias current from a first value to a second value on a reference bit line to the reference memory cell. Further, the method includes comparing reference cell currents on the reference bit line with an operational cell current on the operational bit line to determine a logic state of the selected operational memory cell.

    On-chip calibration circuit and method with half-step resolution
    5.
    发明授权
    On-chip calibration circuit and method with half-step resolution 有权

    公开(公告)号：US10382049B1

    公开(公告)日：2019-08-13

    申请号：US16122993

    申请日：2018-09-06

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric Hunt-Schroeder ,  John A. Fifield

    IPC: H03M1/10 ,  G01R35/00 ,  H03M1/66 ,  H03M1/06

    Abstract: Disclosed is a calibration circuit and method. The circuit includes: a DAC that outputs an analog parameter and includes output parameter adjustment circuitry; a comparator that receives a reference parameter and the analog parameter; and a control circuit (with select logic) connected to the comparator and DAC in a feedback loop. During a calibration mode, the magnitude of the analog parameter is adjusted by ½ DAC step in one direction and the feedback loop is used to perform a binary search calibration process. During an operation mode, the magnitude of the analog parameter is adjusted by ½ DAC step in the opposite direction. The select logic selects the DAC step identified by the calibration process or the next higher DAC step as a final DAC step. The control circuit outputs a final DAC code corresponding to the final DAC step and the DAC generates a calibrated parameter based thereon.

    FINFET fin height control
    6.
    发明授权
    FINFET fin height control 有权
    FINFET翅片高度控制

    公开(公告)号：US09530654B2

    公开(公告)日：2016-12-27

    申请号：US13862819

    申请日：2013-04-15

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Nicholas V. Licausi

    IPC: H01L21/308 ,  H01L21/306 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/3105

    CPC classification number: H01L21/30625 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

    Abstract: Fin height control techniques for FINFET fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate. The isolation material located between fin structures may be selectively removed after treatment to increase its mechanical strength such as by, for example, annealing and curing. A sacrificial material may be deposited over the isolation material between the fin structures in a substantially uniform thickness. The top portion of the fin structures may be selectively removed to achieve a uniform planar surface over the fin structures and sacrificial material. The sacrificial material may then be selectively removed to achieve a uniform fin height relative to the isolation material.

    Abstract translation: 公开了FinFET制造的翅片高度控制技术。 该技术包括一种用于控制多个翅片结构的高度以实现其相对于位于半导体衬底上的翅片结构之间的隔离材料的顶表面的均匀高度的方法。 位于翅片结构之间的隔离材料可以在处理之后选择性地除去以增加其机械强度，例如通过退火和固化。 牺牲材料可以以基本均匀的厚度沉积在翅片结构之间的隔离材料上。 可以选择性地去除翅片结构的顶部以在翅片结构和牺牲材料上实现均匀的平坦表面。 然后可以选择性地去除牺牲材料以实现相对于隔离材料的均匀的翅片高度。

    Body tie test structure for accurate body effect measurement
    7.
    发明授权
    Body tie test structure for accurate body effect measurement 有权
    身体绑带测试结构，用于精确的身体效应测量

    公开(公告)号：US08293606B2

    公开(公告)日：2012-10-23

    申请号：US12973377

    申请日：2010-12-20

    Applicant: Sriram Madhavan ,  Qiang Chen ,  Darin A. Chan ,  Jung-Suk Goo

    Inventor： Sriram Madhavan ,  Qiang Chen ,  Darin A. Chan ,  Jung-Suk Goo

    IPC: H01L27/12

    CPC classification number: H01L29/78615 ,  H01L22/34

    Abstract: A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

    Abstract translation: 提供了一种身体搭接测试结构及其制造方法。 晶体管包括形成在半导体材料层中的主体结合半导体绝缘体（SOI）晶体管，该晶体管包括具有基本恒定的栅极长度L的十字形栅极结构。绝缘阻挡层能够形成间隔区域 所述半导体材料层将所述源极和漏极区域与所述主体连接区域分开。 具有与本征晶体管主体基本上相同的反转特性的导电沟道通过间隔区将主体连接到本征晶体管本体。

    Contact structures and methods of making the contact structures
    8.
    发明授权
    Contact structures and methods of making the contact structures 有权

    公开(公告)号：US10381354B2

    公开(公告)日：2019-08-13

    申请号：US15861161

    申请日：2018-01-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Daniel Chanemougame ,  Emilie Bourjot

    IPC: H01L27/11 ,  H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

    Abstract: One illustrative IC product disclosed herein includes a first merged doped source/drain region that includes first and second doped regions and an isolation structure positioned adjacent the first doped region. In this example, the product also includes a contact structure positioned adjacent the isolation structure, wherein the contact structure includes a first portion positioned below an upper surface of the first merged doped source/drain region and a second portion positioned above the upper surface, wherein the first portion physically contacts both the first and second doped regions. The product also includes a layer of insulating material positioned on and in physical contact with a portion of an upper surface of the first portion of the contact structure.

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