公开(公告)号：US08897077B2

公开(公告)日：2014-11-25

申请号：US13715469

申请日：2012-12-14

申请人： Genusion, Inc.

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

IPC分类号： G11C16/10 ,  H01L27/115 ,  G11C16/12 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/12 ,  H01L27/115 ,  H01L27/11524

摘要： According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.

摘要翻译： 根据本发明的一个方面，提供一种非易失性半导体存储器件，包括：沿第一方向布置的多个位线; 沿所述第一方向布置的多条源极线，所述多条源极线与所述多个位线平行，所述多个源极线与所述多个位线不同; 沿垂直于第一方向的第二方向布置的多个存储栅极线; 多个存储单元，以矩阵形式布置，所述多个存储单元中的每一个包括具有第一端子，第二端子，第一端子和第二端子之间的通道的ap型MIS非易失性晶体管，形成在栅极绝缘膜上的栅极绝缘膜 连接到所述多个存储栅极线中的一个对应的存储栅极线的栅极，以及形成在所述栅极绝缘膜和所述栅电极之间的载流子存储层，所述第一端子连接到所述多个栅极线中的一个相应的位线 位线，并且所述第二端子连接到所述多个源极线中的一个对应的源极线。

公开(公告)号：US08044498B2

公开(公告)日：2011-10-25

申请号：US12164503

申请日：2008-06-30

申请人： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

发明人： Moriyoshi Nakashima ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC分类号： H01L23/07

CPC分类号： H01L25/0657 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06596 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012

摘要： A semiconductor device can be manufactured with a high non-defect ratio, making it possible to easily guarantee the KGD (Known-Good-Die) of semiconductor chips, when configuring one packaged semiconductor device on which a plurality of semiconductor chips is mounted. Utilizing each semiconductor chip is made possible without limits on terminal position, pitch, signal arrangement, and so on.Protrusions provided to a semiconductor chip mounted sealing sub-board are attached to a package substrate. A plurality of semiconductor bare chips is disposed in a space formed between the semiconductor chip mounted sealing sub-board and the package substrate, making wiring possible.

摘要翻译： 可以制造具有高无缺陷率的半导体器件，使得可以在配置其上安装有多个半导体芯片的一个封装的半导体器件时容易地保证半导体芯片的KGD（已知好裸芯片）。 使得每个半导体芯片可以在终端位置，间距，信号布置等方面没有限制。 提供给半导体芯片安装的密封子板的突起附接到封装基板。 多个半导体裸芯片设置在形成在半导体芯片安装密封子板和封装基板之间的空间中，使得布线成为可能。

公开(公告)号：US07969780B2

公开(公告)日：2011-06-28

申请号：US11776491

申请日：2007-07-11

申请人： Taku Ogura ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Taku Ogura ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C11/34 ,  G11C14/00

CPC分类号： G11C11/412 ,  G11C14/00 ,  G11C14/0063

摘要： An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters including memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

摘要翻译： 本发明的目的是提供一种可以具有宽的读取余量的可重写非易失性存储单元，并且可以通过改变Vcc的电平来控制字线和位线。 作为解决方案，触发器是通过包括存储晶体管的逆变器的交叉（环路）连接形成的，所述存储器晶体管可以通过电荷注入到晶体管的侧面间隔来控制阈值电压。 在向一个存储晶体管写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极，并且通过另一侧反相器的负载晶体管将高电压提供给存储晶体管的栅极。 在擦除写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极。

公开(公告)号：US20090175083A1

公开(公告)日：2009-07-09

申请号：US11684035

申请日：2007-03-09

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US20140040537A1

公开(公告)日：2014-02-06

申请号：US13955493

申请日：2013-07-31

申请人： GENUSION INC.

发明人： Moriyoshi NAKASHIMA ,  Junichi IKEGAMI

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F21/79 ,  G06F2212/7205 ,  G06F2221/2137 ,  G06F2221/2143

摘要： A storage medium using a nonvolatile semiconductor storage device for preventing an inadvertent file leak as much as possible is provided. A storage medium using a nonvolatile semiconductor storage device includes a control unit for writing data to memory cells which store data corresponding to files stored on the storage medium, such that all the memory cells are put into the same electronic state, or for erasing data from the memory cells, after a lapse of a set time period.

摘要翻译： 提供一种使用非易失性半导体存储装置的存储介质，用于尽可能地防止无意的文件泄漏。 使用非易失性半导体存储装置的存储介质包括用于将数据写入存储单元的控制单元，存储单元存储对应于存储在存储介质上的文件的数据，使得所有存储单元都被放入同一电子状态，或者用于从 存储器单元，经过一段设定的时间段。

公开(公告)号：US08339862B2

公开(公告)日：2012-12-25

申请号：US12343552

申请日：2008-12-24

申请人： Natsuo Aiika ,  Shoii Shukuri ,  Satoshi Shimizu ,  Taku Ogura

发明人： Natsuo Aiika ,  Shoii Shukuri ,  Satoshi Shimizu ,  Taku Ogura

IPC分类号： G11C16/06 ,  G11C11/34 ,  H01L29/792

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/12 ,  H01L27/115 ,  H01L27/11524

摘要： According to an aspect of the present invention, it is provided: a nonvolatile semiconductor memory device comprising: a plurality of bit lines arranged in a first direction; a plurality of source lines arranged in the first direction, the plurality of source lines being parallel to the plurality of bit lines, the plurality of source lines being distinct from the plurality of bit lines; a plurality of memory gate lines arranged in a second direction perpendicular to the first direction; a plurality of memory cells arranged in a matrix, each of the plurality of memory cells including a p type MIS nonvolatile transistor having a first terminal, a second terminal, a channel between the first terminal and the second terminal, a gate insulation film formed on the channel, a gate electrode connected to one corresponding memory gate line of the plurality of memory gate lines, and a carrier storage layer formed between the gate insulation film and the gate electrode, the first terminal being connected to one corresponding bit line of the plurality of bit lines and the second terminal being connected to one corresponding source line of the plurality of source lines.

摘要翻译： 根据本发明的一个方面，提供一种非易失性半导体存储器件，包括：沿第一方向布置的多个位线; 沿所述第一方向布置的多条源极线，所述多条源极线与所述多个位线平行，所述多个源极线与所述多个位线不同; 沿垂直于第一方向的第二方向布置的多个存储栅极线; 多个存储单元，以矩阵形式布置，所述多个存储单元中的每一个包括具有第一端子，第二端子，第一端子和第二端子之间的通道的ap型MIS非易失性晶体管，形成在栅极绝缘膜上的栅极绝缘膜 连接到所述多个存储栅极线中的一个对应的存储栅极线的栅极，以及形成在所述栅极绝缘膜和所述栅电极之间的载流子存储层，所述第一端子连接到所述多个栅极线中的一个相应的位线 位线，并且所述第二端子连接到所述多个源极线中的一个对应的源极线。

公开(公告)号：US08106443B2

公开(公告)日：2012-01-31

申请号：US12246193

申请日：2008-10-06

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Taku Ogura

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  G11C16/0441 ,  G11C16/0491 ,  H01L21/26586 ,  H01L29/792

摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.

摘要翻译： 非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部 所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层， 形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散 肋骨中的结构是不对称的。

公开(公告)号：US08017994B2

公开(公告)日：2011-09-13

申请号：US12499220

申请日：2009-07-08

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

IPC分类号： H01L29/792

CPC分类号： G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568

摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

公开(公告)号：US20090310409A1

公开(公告)日：2009-12-17

申请号：US12499220

申请日：2009-07-08

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Moriyoshi Nakashima

IPC分类号： G11C16/04 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/12 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11568

摘要： A hot electron (BBHE) is generated close to a drain by tunneling between bands, and it data writing is performed by injecting the hot electron into a charge storage layer. When Vg is a gate voltage, Vsub is a cell well voltage, Vs is a source voltage and Vd is a drain voltage, a relation of Vg>Vsub>Vs>Vd is satisfied, Vg−Vd is a value of a potential difference required for generating a tunnel current between the bands or higher, and Vsub−Vd is substantially equivalent to a barrier potential of the tunnel insulating film or higher.

摘要翻译： 通过在带之间隧穿，在漏极附近产生热电子（BBHE），并且通过将热电子注入电荷存储层来进行数据写入。 当Vg为栅极电压时，Vsub为单元阱电压，Vs为源极电压，Vd为漏极电压，满足Vg> Vsub> Vs> Vd的关系，Vg-Vd为需要的电位差的值 用于在带之间产生隧道电流或更高，Vsub-Vd基本上等于隧道绝缘膜的势垒电位或更高。

公开(公告)号：US20090065922A1

公开(公告)日：2009-03-12

申请号：US12235734

申请日：2008-09-23

申请人： Moriyoshi NAKASHIMA ,  Kazuo Kobayashi ,  Natsuo Ajika

发明人： Moriyoshi NAKASHIMA ,  Kazuo Kobayashi ,  Natsuo Ajika

IPC分类号： H01L23/02

CPC分类号： H01L23/3135 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip mounted interposer (60) is configured by executing wire bonding between a semiconductor chip (50) and an interposer (20), in which terminals (21) that connect to terminals (51) of the chip (50) and separate terminals (22) are formed, on the upper face of the interposer (20). A semiconductor chip (30) is mounted to the top face of a package substrate (10), the interposer (60) is adhered to the upper portion of the chip (30), and wire bonding is executed between the terminals (22) and terminals (11′). When configuring a semiconductor device with a plurality of semiconductor chips combined into one package in this manner, KGD (Known-Good-Die) can easily be guaranteed for each semiconductor chip, and semiconductor devices can be fabricated with a high yield of good units. Also, the semiconductor chips can be used as-is, without restricting the position, pitch, signal arrangement, or the like, of their terminals.

摘要翻译： 半导体芯片安装插入件（60）通过在半导体芯片（50）和插入件（20）之间执行引线键合而构成，其中连接到芯片（50）的端子（51）的端子（21）和分离的端子 （22）形成在插入件（20）的上表面上。 半导体芯片（30）安装在封装基板（10）的顶面上，插入件（60）粘接到芯片（30）的上部，并且在端子（22）和 端子（11'）。 当以这种方式配置具有组合成一个封装的多个半导体芯片的半导体器件时，可以容易地保证每个半导体芯片的KGD（Known-Good-Die），并且可以以高产量的良好单元制造半导体器件。 此外，半导体芯片可以原样使用，而不限制其端子的位置，间距，信号布置等。