公开(公告)号：US09083373B2

公开(公告)日：2015-07-14

申请号：US14135156

申请日：2013-12-19

Applicant: STMicroelectronics International, N.V.

Inventor： MunishKumar Mangal ,  Ranajay Mallik

IPC: H03M11/00 ,  H03M1/30 ,  H04L27/22

CPC classification number: H03M1/303 ,  H03M1/305 ,  H03M1/306 ,  H04L27/22

Abstract: A system and method for decoding quadrature signals includes a quadrature signal generator, a quadrature signal decoder, a key matrix and a driver. The quadrature signal generator generates quadrature signals on rotation. The quadrature signal decoder is configured to convert the quadrature signals into non-overlapping signals. The key matrix is configured to receive the non-overlapping signals. The driver is configured to scan the key matrix to decode the non-overlapping signals to generate an event update corresponding to a direction of rotation of the quadrature signal generator.

Abstract translation: 用于解码正交信号的系统和方法包括正交信号发生器，正交信号解码器，密钥矩阵和驱动器。 正交信号发生器在旋转时产生正交信号。 正交信号解码器被配置为将正交信号转换成非重叠信号。 密钥矩阵被配置为接收不重叠的信号。 驱动器被配置为扫描键矩阵以解码不重叠的信号以产生对应于正交信号发生器的旋转方向的事件更新。

公开(公告)号：US08767428B2

公开(公告)日：2014-07-01

申请号：US13172665

申请日：2011-06-29

Applicant: Vivek Asthana

Inventor： Vivek Asthana

IPC: G11C15/00

CPC classification number: G11C5/147 ,  G11C11/417

Abstract: A memory bank includes memory cells and an additional cell to determine an operating voltage of the memory bank. The additional cell has an operating margin that is less than a corresponding operating margin of the other memory cells in the memory bank.

Abstract translation: 存储器体包括存储器单元和用于确定存储体的工作电压的附加单元。 附加单元具有小于存储体中其它存储单元的对应操作裕度的操作裕度。

公开(公告)号：US08705624B2

公开(公告)日：2014-04-22

申请号：US12625305

申请日：2009-11-24

Applicant: Amit Gupta ,  Srijib Narayan Maiti

Inventor： Amit Gupta ,  Srijib Narayan Maiti

IPC: H04N7/12

CPC classification number: H04N19/436 ,  H04N19/176 ,  H04N19/31 ,  H04N19/33 ,  H04N19/44

Abstract: A method for decoding a stream encoded using a scalable video coding and including a plurality of layers of frames divided into a plurality of blocks, decodes block-wise in parallel the layers of the stream. A target block in an enhancement layer is decoded as soon as the block data required for its decoding are available from the reference layer.

Abstract translation: 一种用于解码使用可分级视频编码并且包括划分成多个块的多个帧的帧的流的解码方法，并行地逐行解码流的层。 一旦增强层中的目标块可以从参考层获得，解码所需的块数据就被解码。

公开(公告)号：US08549370B2

公开(公告)日：2013-10-01

申请号：US12982611

申请日：2010-12-30

Applicant: Parul Bansal

Inventor： Parul Bansal

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G06F11/3656

Abstract: An on-chip functional debugger includes one or more functional blocks each providing one or more functional outputs. A hierarchical selection tree is formed by one or more selectors having the output of one of the selectors as a final output and individual selector inputs coupled either to a functional output from the functional blocks or to an output of another selector. A selection signal coupled to the select input of each of the selectors to enable a selected one of its output. An output node coupled to the final output. A method of providing on-chip functional debugging is also provided. A desired functional output from one or more available functional outputs is selected and then the selected functional output is coupled to an output node.

Abstract translation: 片上功能调试器包括一个或多个功能块，每个功能块提供一个或多个功能输出。 分层选择树由具有选择器之一的输出的一个或多个选择器形成为最终输出，以及耦合到功能块的功能输出或另一个选择器的输出的单独选择器输入。 选择信号，其耦合到每个选择器的选择输入以使得其输出中的所选择的一个。 耦合到最终输出的输出节点。 还提供了一种提供片上功能调试的方法。 选择来自一个或多个可用功能输出的期望的功能输出，然后所选择的功能输出耦合到输出节点。

公开(公告)号：US20240377539A1

公开(公告)日：2024-11-14

申请号：US18651950

申请日：2024-05-01

Applicant: STMicroelectronics International N. V.

Inventor： Olivier Lemarchand ,  Ulysse Gaffet ,  Robin Vassal

IPC: G01S17/894 ,  G02B27/00 ,  G06V10/82

Abstract: The present disclosure relates to a system includes a microcontroller including a neural network, a time-of-flight sensor including a plurality of pixels and configured to perform a capture of a scene comprising a user, the capture comprising, for each pixel, the measurement of a distance from the user and of a signal value. The sensor is further configured to calculate a value of a standard deviation associated with the distance value, and a value of a standard deviation associated with the signal value and a confidence value. The sensor is further configured to provide the values to the neural network. The neural network is configured to generate, based on the values, an estimate of a direction associated with the user. The system further includes a display, the microcontroller is configured to control the display, or another circuit, based on the estimate.

公开(公告)号：US12125533B2

公开(公告)日：2024-10-22

申请号：US17812122

申请日：2022-07-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics International N.V.

Inventor： Francesco La Rosa ,  Marco Bildgen

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35

CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H10B41/35

Abstract: In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.

公开(公告)号：US20250117651A1

公开(公告)日：2025-04-10

申请号：US18910448

申请日：2024-10-09

Applicant: STMicroelectronics International N. V.

Inventor： Pierre Demaj ,  Laurent Folliot

IPC: G06N3/08

Abstract: According to one aspect, a computer-implemented method compiles a first trained artificial neural network comprising at least one succession of layers including a depthwise convolutional layer, a saturated rectified linear unit layer, and a two-dimensional convolutional layer. The method comprises equalizing between layers, replacing the saturated rectified linear unit layer with an adaptive channel pruning layer to obtain an artificial neural network with a modified topology, tensor quantizing the layers of the artificial neural network with the modified topology, and compiling the quantized artificial neural network with the modified topology.

公开(公告)号：US20240120933A1

公开(公告)日：2024-04-11

申请号：US18371723

申请日：2023-09-22

Applicant: STMicroelectronics International N. V.

Inventor： Sandrine NICOLAS ,  Danika PERRIN ,  Jean-Baptiste CASANOVA

IPC: H03M1/38

CPC classification number: H03M1/38

Abstract: The present description concerns a method of controlling an analog-to-digital converter, wherein most significant bits are determined by successive approximations implementing a first digital-to-analog converter and a second digital-to-analog converter. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of the first converter with a third digital-to-analog converter and by applying a second ramp to the output of the second converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first and second converters at the end of the successive approximations.

公开(公告)号：US20230170006A1

公开(公告)日：2023-06-01

申请号：US18056803

申请日：2022-11-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N. V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC: G11C7/24 ,  G11C7/10

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1069

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US08560999B2

公开(公告)日：2013-10-15

申请号：US12982570

申请日：2010-12-30

Applicant: Sachin Mathur

Inventor： Sachin Mathur

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method for designing an electronic circuit including determining at least one hold violation in a net routing; inserting a routing blockage associated with each at least one hold violation; de-routing the determined net-routing and re-routing the determined net-routing dependent on at least the routing blockage.

Abstract translation: 一种用于设计电子电路的方法，包括确定网络路由中的至少一个保持违规; 插入与每个至少一个保持违例相关联的路由阻塞; 至少路由阻塞取决于确定的网络路由并重新路由确定的网络路由。