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    TRANSISTORS WITH METAL GATE AND METHODS FOR FORMING THE SAME
    3.
    发明申请
    TRANSISTORS WITH METAL GATE AND METHODS FOR FORMING THE SAME 有权
    具有金属栅的晶体管及其形成方法

    公开(公告)号：US20100155849A1

    公开(公告)日：2010-06-24

    申请号：US12343307

    申请日：2008-12-23

    申请人： Chung-Shi LIU ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

    发明人： Chung-Shi LIU ,  Yung-Sheng Chiu ,  Cheng-Tung Lin ,  Chen-Hua Yu

    IPC分类号： H01L27/092 ,  H01L21/28

    CPC分类号： H01L29/517 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513

    摘要： A semiconductor device includes at least one first gate dielectric layer over a substrate. A first transition-metal oxycarbide (MCxOy) containing layer is formed over the at least one first gate dielectric layer, wherein the transition-metal (M) has an atomic percentage of about 40 at. % or more. A first gate is formed over the first transition-metal oxycarbide containing layer. At least one first doped region is formed within the substrate and adjacent to a sidewall of the first gate.

    摘要翻译： 半导体器件包括在衬底上的至少一个第一栅极电介质层。 在所述至少一个第一栅极介电层上形成含有第一过渡金属碳氧化物（MCxOy）的层，其中所述过渡金属（M）的原子百分比为约40原子。 ％ 或者更多。 在第一过渡金属含碳氧化物层上形成第一栅极。 至少一个第一掺杂区域形成在衬底内并且邻近第一栅极的侧壁。

    Novel method to reduce Rs pattern dependence effect
    4.
    发明申请
    Novel method to reduce Rs pattern dependence effect 有权
    降低Rs模式依赖效应的新方法

    公开(公告)号：US20050085066A1

    公开(公告)日：2005-04-21

    申请号：US10687183

    申请日：2003-10-16

    申请人： Jung-Chih Tsao ,  Chi-Wen Li ,  Kei-Wei Chen ,  Jye-Wei Hsu ,  Hsien-Pin Fong ,  Steven Lin ,  Ray Chuang

    发明人： Jung-Chih Tsao ,  Chi-Wen Li ,  Kei-Wei Chen ,  Jye-Wei Hsu ,  Hsien-Pin Fong ,  Steven Lin ,  Ray Chuang

    IPC分类号： H01L21/22 ,  H01L21/288 ,  H01L21/38 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/288 ,  H01L21/7684

    摘要： A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness t1 is formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness t2 where t2≦t1 and having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (GD1)≧GD2 for the second copper layer.

    摘要翻译： 描述了在图案内的开口中形成铜互连的方法。 铜互连具有几乎独立于开口宽度和图案密度的Rs。 通过沉积铜并执行第一CMP步骤，在电介质层中的通孔或沟槽中形成具有凹上表面和厚度t 1的第一铜层。 具有厚度为2 的第二铜层，其中具有凸下表面的第二铜层沉积在第一铜层上 通过选择性电镀方法。 对第一和​​第二铜层进行退火，然后第二CMP步骤将第二铜层平坦化成与电介质层共面。 本发明也是由上述铜层构成的铜布线，其中第一铜层具有第二铜层的晶粒密度（G SUB D1）= G D2 D2。

    Smart overlay control
    5.
    发明申请
    Smart overlay control 失效
    智能覆盖控制

    公开(公告)号：US20050071033A1

    公开(公告)日：2005-03-31

    申请号：US10672394

    申请日：2003-09-26

    申请人： Kun-Pi Cheng ,  Hsin-Yuan Chen ,  Yo-Nien Lin ,  Feng-Cheng Chung

    发明人： Kun-Pi Cheng ,  Hsin-Yuan Chen ,  Yo-Nien Lin ,  Feng-Cheng Chung

    IPC分类号： G06F19/00

    CPC分类号： G03F7/70633 ,  G03F7/70525

    摘要： An automatic method to maintain and correct overlay in the fabrication of integrated circuits is described. An overlay control table is automatically generated for lots run through a process tool. An overlay correction is calculated from the overlay control table and sent to the process tool for real-time or manual overlay correction.

    摘要翻译： 描述了在集成电路的制造中维护和校正覆盖的自动方法。 自动生成覆盖控制表，用于批处理工具。 从覆盖控制表计算覆盖校正，并发送到过程工具进行实时或手动叠加校正。

    Web service and method for customers to define their own alert for real-time production status
    6.
    发明申请
    Web service and method for customers to define their own alert for real-time production status 有权
    Web服务和方法为​​客户定义自己的警报实时生产状态

    公开(公告)号：US20050060056A1

    公开(公告)日：2005-03-17

    申请号：US10661792

    申请日：2003-09-12

    申请人： Hsu Ta

    发明人： Hsu Ta

    IPC分类号： G06F19/00 ,  G06Q10/00

    CPC分类号： G06Q10/06

    摘要： An automated method and system that uses a Web service to make real-time production status available to customers from a manufacturing environment. Each time Work in Process (WIP) data is updated from manufacturing execution systems to a central database, a database trigger checks the alert conditions. These conditions are automatically compared to the WIP data to see if the user-defined conditions have been met. If so, a function is called which automatically sends an alert to the customer via the internet and either e-mail, pager, or mobile phone.

    摘要翻译： 一种使用Web服务从制造环境向客户提供实时生产状态的自动化方法和系统。 每次在制品（WIP）数据从制造执行系统更新到中央数据库时，数据库触发器将检查警报条件。 这些条件将自动与WIP数据进行比较，以查看是否满足用户定义的条件。 如果是这样，则调用一种功能，它通过互联网，电子邮件，寻呼机或移动电话自动向客户发送警报。

    Shared contact for high-density memory cell design
    7.
    发明申请
    Shared contact for high-density memory cell design 有权
    共享接触高密度存储单元设计

    公开(公告)号：US20040256732A1

    公开(公告)日：2004-12-23

    申请号：US10600315

    申请日：2003-06-20

    申请人： Taiwan Semicondutor Manufacturing Co.

    发明人： Jhon-Jhy Liaw

    IPC分类号： H01L023/48

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： A new method and structure is created for a multi-transistor SRAM device. Standard processing steps are followed for the creation of CMOS devices of providing a patterned layer of gate material, of performing LDD impurity implants, of creating gate spacers. After the creation of the gate spacers, a new step of photoresist patterning and exposure is added. The mask for this additional step is a modified butt-contact mask, comprising enlarging the conventional butt-contact opening by between about 0.005 nullm and 0.2 nullm, an effect that can also be achieved by photo over-expose. This modified butt-contact mask exposes a spacer that is adjacent to the butt-contact hole, this spacer is removed. S/D impurity implant is performed after which conventional processing steps are applied for completion of the multi-transistor SRAM device.

    摘要翻译： 为多晶体管SRAM器件创建了一种新的方法和结构。 遵循标准处理步骤，以创建提供栅极材料的图案化层，执行LDD杂质植入物的CMOS器件，产生栅极间隔物。 在形成栅极间隔物之后，添加光刻胶图案化和曝光的新步骤。 用于该附加步骤的掩模是改进的对接接触掩模，包括将常规对接接触开口扩大约0.005μm至0.2μm，这也可以通过曝光过度曝光实现。 该修改的对接接触掩模暴露与邻接孔相邻的间隔物，该间隔物被去除。 执行S / D杂质注入，之后应用传统的处理步骤来完成多晶体管SRAM器件。

    Edge peeling improvement of low-k dielectric materials stack by adjusting EBR resistance
    8.
    发明申请
    Edge peeling improvement of low-k dielectric materials stack by adjusting EBR resistance 有权
    通过调整EBR电阻来降低低k电介质材料的边缘剥离

    公开(公告)号：US20040248426A1

    公开(公告)日：2004-12-09

    申请号：US10455037

    申请日：2003-06-05

    申请人： Taiwan Semicondutor Manufacturing Co.

    发明人： Tzu-Jen Chou ,  Syun-Ming Jang ,  Ying-Ho Chen ,  Shen-Nan Lee

    IPC分类号： H01L021/31 ,  H01L021/469

    CPC分类号： H01L21/31053 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/76835 ,  H01L21/7684

    摘要： A new method and structure is provided for the polishing of the surface of a layer of low-k dielectric material. Low-k dielectric material of low density and relatively high porosity is combined with low-k dielectric material of high density and low porosity whereby the latter high density layer is, prior to polishing of the combined layers, deposited over the former low density layer. Polishing of the combined layers removes flaking of the polished low-k layers of dielectric. This method can further be extended by forming conductive interconnects through the layers of dielectric, prior to the layer of dielectric.

    摘要翻译： 提供了一种用于抛光低k电介质材料层的表面的新方法和结构。 低密度和相对高孔隙率的低k电介质材料与高密度和低孔隙率的低k电介质材料组合，由此后者的高密度层在组合层的抛光之前沉积在前者的低密度层上。 组合层的抛光消除抛光的低k层电介质的剥落。 在电介质层之前，可以通过在电介质层之间形成导电互连来进一步延长该方法。