公开(公告)号：US20160118265A1

公开(公告)日：2016-04-28

申请号：US14988895

申请日：2016-01-06

Applicant: The Board of Trustees of the University of Illinois

Inventor： Lynford Goddard ,  Kaiyuan Wang ,  Chris Edwards ,  Lonna Edwards ,  Xin Yu ,  Gang Logan Liu ,  Samuel Washington ,  Shailendra Srivastava ,  Terry Koker ,  Julianne Lee ,  Catherine Britt Carlson

IPC: H01L21/306 ,  H01L31/0236 ,  H01L21/768 ,  H01L31/0232

CPC classification number: H01L21/30604 ,  B81C1/00103 ,  B81C1/00111 ,  B81C1/00119 ,  B81C1/00214 ,  B81C1/00484 ,  B81C1/00539 ,  B81C1/00595 ,  B81C2201/0114 ,  B81C2201/0139 ,  B81C2201/0157 ,  C25F3/12 ,  C25F3/14 ,  G01B11/2441 ,  H01L21/30617 ,  H01L21/3063 ,  H01L21/76886 ,  H01L22/12 ,  H01L31/02327 ,  H01L31/02363

Abstract: Methods and apparatus for subtractively fabricating three-dimensional structures relative to a surface of a substrate and for additively depositing metal and dopant atoms onto the surface and for diffusing them into the bulk. A chemical solution is applied to the surface of the semiconductor substrate, and a spatial pattern of electron-hole pairs is generated by projecting a spatial pattern of illumination characterized by a specified intensity, wavelength and duration at each pixel of a plurality of pixels on the surface. An electrical potential is applied across the interface of the semiconductor and the solution with a specified temporal profile relative to the temporal profile of the spatial pattern of illumination. Such methods are applied to the fabrication of a photodetector integral with a parabolic reflector, cell size sorting chips, a three-dimensional photonic bandgap chip, a photonic integrated circuit, and an integrated photonic microfluidic circuit.

Abstract translation: 用于相对于衬底的表面相对地制造三维结构并用于在表面上相加地沉积金属和掺杂剂原子并将其扩散到本体中的方法和装置。 将化学溶液施加到半导体衬底的表面，并且通过将在特定强度，波长和持续时间上的特定的照明的空间图案投影在多个像素的每个像素上来产生电子 - 空穴对的空间图案 表面。 相对于照明的空间模式的时间分布，电势跨越半导体和解决方案的界面以特定的时间分布被施加。 这种方法适用于与抛物面反射器，单元尺寸分选芯片，三维光子带隙芯片，光子集成电路和集成光子微流体电路集成的光电检测器的制造。

公开(公告)号：US09708182B2

公开(公告)日：2017-07-18

申请号：US14838988

申请日：2015-08-28

Applicant: Infineon Technologies AG

Inventor： Andreas Behrendt ,  Kai-Alexander Schreiber ,  Sokratis Sgouridis ,  Martin Zgaga ,  Bernhard Winkler

IPC: H01L21/00 ,  B81C1/00 ,  B81B3/00 ,  H01L21/3063

CPC classification number: B81C1/00531 ,  B81B3/0021 ,  B81B3/0094 ,  B81B2203/033 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0139 ,  H01L21/3063

Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

公开(公告)号：US08426235B2

公开(公告)日：2013-04-23

申请号：US13319970

申请日：2010-05-13

Applicant: Chienliu Chang

Inventor： Chienliu Chang

IPC: H01L21/02

CPC classification number: B06B1/0292 ,  B81B2201/0271 ,  B81B2203/0127 ,  B81C1/00476 ,  B81C2201/0139

Abstract: A capacitive electromechanical transducer includes a substrate, a cavity formed by a vibrating membrane held above the substrate with a certain distance between the vibrating membrane and the substrate by supporting portions arranged on the substrate, a first electrode whose surface is exposed to the cavity, and a second electrode whose surface facing the cavity is covered with an insulating film, wherein the first electrode is provided on a surface of the substrate or a lower surface of the vibrating membrane and the second electrode is provided on a surface of the vibrating membrane or a surface of the substrate so as to face the first electrode. In this transducer, fine particles composed of an oxide film of a substance constituting the first electrode are arranged on the surface of the first electrode, and the diameter of the fine particles is 2 to 200 nm.

Abstract translation: 一种电容式机电换能器，包括基板，由振动膜形成的空腔，该振动膜通过支撑布置在基板上的部分而在振动膜和基板之间具有一定距离而保持在基板上方，其表面暴露于空腔中的第一电极， 面向空腔的表面的第二电极被绝缘膜覆盖，其中第一电极设置在基板的表面或振动膜的下表面上，第二电极设置在振动膜的表面上或 基板的表面以面对第一电极。 在该换能器中，由构成第一电极的物质的氧化物膜构成的微粒子配置在第一电极的表面上，微粒的直径为2〜200nm。

公开(公告)号：US20040147057A1

公开(公告)日：2004-07-29

申请号：US10473762

申请日：2004-03-30

Inventor： Hubert Benzel ,  Heribert Weber ,  Frank Schaefer

IPC: H01L021/00

CPC classification number: B81C1/00047 ,  B81B2201/0278 ,  B81C2201/0115 ,  B81C2201/0139

Abstract: A method for manufacturing a semiconductor component (100; . . . ; 700), a multilayer semiconductor component in particular, preferably a micromechanical component, such as a heat transfer sensor in particular having a semiconductor substrate (101), in particular made of silicon, and a sensor region (404). For inexpensive manufacture of a thermal insulation between the semiconductor substrate (101) and the sensor region (404) a porous layer (104; 501) is provided in the semiconductor component (100; . . . ; 700).

Abstract translation: 一种用于制造半导体部件（100 ... ... 700）的方法，特别是多层半导体部件，优选微机械部件，例如特别是具有半导体衬底（101）的传热传感器，特别是由硅 ，和传感器区域（404）。 为了廉价地制造半导体衬底（101）和传感器区域（404）之间的绝热，在半导体部件（100 ... 700）中设置多孔层（104; 501）。

公开(公告)号：US09139427B2

公开(公告)日：2015-09-22

申请号：US13864762

申请日：2013-04-17

Applicant: Infineon Technologies AG

Inventor： Andreas Behrendt ,  Kai-Alexander Schreiber ,  Sokratis Sgouridis ,  Martin Zgaga ,  Bernhard Winkler

IPC: H01L21/311 ,  B81C1/00 ,  B81B3/00 ,  H01L21/3063

CPC classification number: B81C1/00531 ,  B81B3/0021 ,  B81B3/0094 ,  B81B2203/033 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0139 ,  H01L21/3063

Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

Abstract translation: 一种用于在半导体衬底内制造至少一个空腔的方法包括：在半导体衬底的表面在至少一个预定的腔位置干蚀刻半导体衬底，以便获得至少一个临时空腔。 该方法包括在半导体衬底的表面和至少一个临时空腔的空腔表面处沉积关于随后的湿法蚀刻工艺的保护材料。 此外，该方法包括至少在至少一个临时空腔的底部的一部分处去除保护材料以暴露半导体衬底。 接着在至少一个临时腔的底部的暴露部分对半导体衬底进行电化学蚀刻。 还公开了使用这种类型的空腔形成和相应的MEMS的微机械传感器系统的制造方法。

公开(公告)号：US20120058587A1

公开(公告)日：2012-03-08

申请号：US13319970

申请日：2010-05-13

Applicant: Chienliu Chang

Inventor： Chienliu Chang

IPC: H01L21/02

CPC classification number: B06B1/0292 ,  B81B2201/0271 ,  B81B2203/0127 ,  B81C1/00476 ,  B81C2201/0139

Abstract: A capacitive electromechanical transducer includes a substrate, a cavity formed by a vibrating membrane held above the substrate with a certain distance between the vibrating membrane and the substrate by supporting portions arranged on the substrate, a first electrode whose surface is exposed to the cavity, and a second electrode whose surface facing the cavity is covered with an insulating film, wherein the first electrode is provided on a surface of the substrate or a lower surface of the vibrating membrane and the second electrode is provided on a surface of the vibrating membrane or a surface of the substrate so as to face the first electrode. In this transducer, fine particles composed of an oxide film of a substance constituting the first electrode are arranged on the surface of the first electrode, and the diameter of the fine particles is 2 to 200 nm.

Abstract translation: 一种电容式机电换能器，包括基板，由振动膜形成的空腔，该振动膜通过支撑布置在基板上的部分而在振动膜和基板之间具有一定距离而保持在基板上方，其表面暴露于空腔中的第一电极， 面向空腔的表面的第二电极被绝缘膜覆盖，其中第一电极设置在基板的表面或振动膜的下表面上，第二电极设置在振动膜的表面上或 基板的表面以面对第一电极。 在该换能器中，由构成第一电极的物质的氧化物膜构成的微粒子配置在第一电极的表面上，微粒的直径为2〜200nm。

公开(公告)号：US20080245674A1

公开(公告)日：2008-10-09

申请号：US12040378

申请日：2008-02-29

Applicant: Robert J. von Gutfeld ,  Alan C. West

Inventor： Robert J. von Gutfeld ,  Alan C. West

IPC: B05D5/04

CPC classification number: C25F3/02 ,  B81C1/00571 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/0142 ,  C23F1/02 ,  C23F1/08 ,  H05K3/068 ,  H05K2203/1105 ,  H05K2203/1115

Abstract: Systems and methods for etching topographic features in non-crystalline or metallic substrates are provided. A protective material is placed and patterned on a surface of the substrate to define exposed and protected regions of the substrate for etching in a liquid etchant having etching rates that are thermally activated. A nonuniform temperature profile is imposed on the substrate so that the temperatures and hence the etching rates at surfaces in the exposed regions are higher than those in the protected regions. Arrangements for imposing the nonuniform temperature profile include heating designated portions of the substrate with light radiation. Alternatively, the non-uniform temperature profile is developed as etching progresses by passing current pulses through the substrate in a manner that causes geometrically non-uniform heating of the substrate.

Abstract translation: 提供用于蚀刻非晶体或金属基底中的地形特征的系统和方法。 保护材料被放置并图案化在衬底的表面上以限定衬底的暴露和保护区域，以在具有热激活蚀刻速率的液体蚀刻剂中蚀刻。 对基板施加不均匀的温度曲线，使得暴露区域中的表面的温度和蚀刻速率高于受保护区域中的温度。 施加不均匀温度分布的布置包括用光辐射加热衬底的指定部分。 或者，当通过使电流脉冲以导致衬底的几何不均匀加热的方式通过衬底时蚀刻进行蚀刻而开发不均匀的温度分布。

公开(公告)号：US07153440B2

公开(公告)日：2006-12-26

申请号：US10242213

申请日：2002-09-12

Applicant: Bevan Staple ,  Jillian Buriak

Inventor： Bevan Staple ,  Jillian Buriak

IPC: C23F1/00

CPC classification number: B82Y30/00 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0114 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/053

Abstract: A microelectromechanical structure is formed by depositing sacrificial and structural material over a substrate to form a structural layer on a component electrically attached with the substrate. The galvanic potential of the structural layer is greater than the galvanic potential of the component. At least a portion of the structural material is covered with a protective material that has a galvanic potential less than or equal to the galvanic potential of the component. The sacrificial material is removed with a release solution. At least one of the protective material and release solution is surfactanated, the surfactant functionalizing a surface of the component.

公开(公告)号：US06399177B1

公开(公告)日：2002-06-04

申请号：US09580105

申请日：2000-05-30

Applicant: Stephen J. Fonash ,  Ali Kaan Kalkan ,  Sanghoon Bae

Inventor： Stephen J. Fonash ,  Ali Kaan Kalkan ,  Sanghoon Bae

IPC: B32B700

CPC classification number: B81C1/0038 ,  B81C1/00047 ,  B81C2201/0115 ,  B81C2201/0139 ,  B81C2201/018 ,  C23C16/24 ,  C23C16/511 ,  G01N21/17 ,  G01N27/121 ,  G01N27/44717 ,  G01N30/6095 ,  H01J49/0418 ,  Y10T428/24174 ,  Y10T428/249953

Abstract: A novel porous film is disclosed comprising a network of silicon columns in a continuous void which may be fabricated using high density plasma deposition at low temperatures, i.e., less than about 250° C. This silicon film is a two-dimensional nano-sized array of rodlike columns. This void-column morphology can be controlled with deposition conditions and the porosity can be varied up to 90%. The simultaneous use of low temperature deposition and etching in the plasma approach utilized, allows for the unique opportunity of obtaining columnar structure, a continuous void, and polycrystalline column composition at the same time. Unique devices may be fabricated using this porous continuous film by plasma deposition of this film on a glass, metal foil, insulator or plastic substrates.

Abstract translation: 公开了一种新颖的多孔膜，其包括在连续空隙中的硅柱网络，其可以在低温下（即小于约250℃）下使用高密度等离子体沉积来制造。该硅膜是二维纳米尺寸阵列 的棒状柱。 这种空隙柱形态可以用沉积条件控制，并且孔隙率可以变化高达90％。 在所采用的等离子体方法中同时使用低温沉积和蚀刻允许在同时获得柱状结构，连续空隙和多晶柱组成的独特机会。 可以使用这种多孔连续膜通过将该膜等离子体沉积在玻璃，金属箔，绝缘体或塑料基底上来制造独特的器件。

公开(公告)号：US20190023563A1

公开(公告)日：2019-01-24

申请号：US15757672

申请日：2016-09-09

Applicant: DENSO CORPORATION

Inventor： Akira OGAWA ,  Yoshitaka NODA ,  Tetsuo YOSHIOKA ,  Yuhei SHIMIZU

IPC: B81C1/00

CPC classification number: B81C1/00579 ,  B81B2201/033 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0139 ,  B81C2201/0142 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0882

Abstract: A semiconductor device production method includes performing trench etching to form a trench in a thickness direction of a semiconductor layer so that both of a first pattern portion and a second pattern portion whose side walls face each other across the trench are formed. In the trench etching, the semiconductor layer is etched and removed while a protective film is formed on a surface of the semiconductor layer, and the trench etching is performed so that the first pattern portion and the second pattern portion are configured to have a same potential or a same temperature during the trench etching.