BALANCING LOSSES IN SEMICONDUCTOR OPTICAL WAVEGUIDES

    公开(公告)号:US20230194906A1

    公开(公告)日:2023-06-22

    申请号:US16957309

    申请日:2018-12-21

    Inventor: Selina FARWELL

    CPC classification number: G02F1/0123 G02F1/025 G02F1/0156 G02F1/0157

    Abstract: A method of equalising optical losses, at a required operating wavelength, in waveguide sections in an optoelectronic device comprising a first semiconductor waveguide section and a second semiconductor waveguide section, the method comprising determining (1301) a first optical loss through the first waveguide section for a signal with the required operating wavelength, determining (1302) a second optical loss through the second waveguide section for the signal, determining (1303) a loss difference between the first optical loss and the second optical loss, determining (1304) a first bias voltage based on the loss difference and the operating wavelength, such that the loss difference is reduced, and applying (1305) the bias voltage to the first waveguide section.

    Optical module
    5.
    发明授权

    公开(公告)号:US12027815B2

    公开(公告)日:2024-07-02

    申请号:US17223093

    申请日:2021-04-06

    Inventor: Osamu Kagaya

    CPC classification number: H01S5/0085 G02F1/0157 H01P3/08

    Abstract: Each semiconductor device includes a semiconductor laser unit and an optical modulator unit. Each transmission line is configured to transmit a drive signal to the optical modulator unit. Each resistor is provided for the transmission line and configured to terminate the drive signal. Each first conductive pattern is connected to one electrode of the semiconductor laser unit and one electrode of the optical modulator unit. Each chip capacitor has one electrode connected to another electrode of the semiconductor laser unit through a bonding wire. Each chip capacitor has another electrode connected to the first conductive pattern that is connected to the semiconductor laser unit. Each second conductive pattern is connected to the resistor, directly or through a DC blocking capacitor. Each third conductive pattern is connected to each of the first conductive pattern and the second conductive pattern through a conductive via hole in the chip carrier.

    THERMAL CONTROL OF AN OPTICAL COMPONENT
    7.
    发明公开

    公开(公告)号:US20240145328A1

    公开(公告)日:2024-05-02

    申请号:US18123170

    申请日:2023-03-17

    Inventor: Subal Sahni

    CPC classification number: H01L23/34 G02F1/0157 H01L25/167

    Abstract: The present disclosure relates to thermal control systems, photonic memory fabrics, and electro-absorption modulators (EAMs). For example, the thermal control systems efficiently move data in a memory fabric based on utilizing and controlling thermally controlling optical components. As another example, the EAMs are instances of optical modulators used to efficiently move data within digital circuits while maintaining thermally-stable optical modulation across a wide temperature range.

    Stacked-dies optically bridged multicomponent package

    公开(公告)号:US12130485B1

    公开(公告)日:2024-10-29

    申请号:US18610431

    申请日:2024-03-20

    Abstract: An implementation provides a package that includes a first die including a bridging element, an analog/mixed-signal (AMS) die, and a general die. The first die includes: a first photonic transceiver portion, a first die first interconnect region, and an optical interface (OI). The AMS die includes a second photonic transceiver portion, an AMS die first interconnect region on a first surface of the AMS die electrically and physically coupled with the first die first interconnect region; and an AMS die second interconnect region on a second surface of the AMS die. The general die includes a third photonic transceiver portion, and a general die first interconnect region electrically and physically coupled with the second photonic transceiver portion.

    MULTICOMPONENT PHOTONICALLY INTRA-DIE BRIDGED ASSEMBLY

    公开(公告)号:US20240272393A1

    公开(公告)日:2024-08-15

    申请号:US18632658

    申请日:2024-04-11

    Abstract: A package includes a first die with a compute element and first region, a second die with a compute element and second region, and a bridging element connecting the first and second dies. The bridging element includes interconnect regions for electrical coupling, a first photonic path from the first interconnect region to the second, and a second photonic path in the reverse direction. A photonic transceiver is integrated into the bridging element, with one portion sending and receiving optical signals via the photonic paths, and the other portion located in an AMS block in the first die or second die near the memory and compute elements. The transceiver portions are connected by a short electrical interconnect (less than 2 mm).

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