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    THERMAL MITIGATION SYSTEMS AND METHODS FOR MULTI-CORE PROCESSORS
    5.
    发明公开
    THERMAL MITIGATION SYSTEMS AND METHODS FOR MULTI-CORE PROCESSORS 审中-公开

    公开(公告)号：US20240272698A1

    公开(公告)日：2024-08-15

    申请号：US18168071

    申请日：2023-02-13

    申请人： QUALCOMM INCORPORATED

    发明人： Darshan Kumar NANDANWAR

    IPC分类号： G06F1/324 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/30

    CPC分类号： G06F1/324 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/3058

    摘要： A system for performing thermal mitigation in a multi-core processor determines which processing core(s) of the processor is responsible for causing the temperature to rise to an undesired level and then performs one or more thermal mitigation steps only in the responsible core to avoid degrading performance of the other cores. The system monitors digital activity (DA) of the pipeline stages of the cores, determines when the DA of a processing stage has caused temperature to rise to a particular level and then reduces the DA of at least one processing stage of the responsible core in order to reduce temperature. The system can also take one or more other thermal mitigation steps based on monitored temperature values, such as reducing clock frequency or selecting a different V/F corner of the responsible core.

    Two-wire host interface
    6.
    发明授权
    Two-wire host interface 有权

    公开(公告)号：US12061568B2

    公开(公告)日：2024-08-13

    申请号：US17639417

    申请日：2020-09-11

    申请人： IDEX BIOMETRICS ASA

    发明人： Adrian Wise ,  Keith Ahluwalia

    IPC分类号： G06F13/42 ,  G06F1/3206 ,  G06F13/40

    CPC分类号： G06F13/4286 ,  G06F1/3206 ,  G06F13/4068 ,  G06F13/4291

    摘要： A two-wire interface (300) for connecting a first device (106) and a second device (108). The two-wire interface (300) is operable in a handshaking mode and a data transfer mode. In the handshaking mode the first wire (302) of the interface (300) is driven by the first device (106) and the second wire (304) of the interface (300) is driven by the second device (108) so that the first (106) and second (108) devices can perform a handshaking sequence. In the data transfer mode one of the first wire (302) and the second wire (304) is driven by one of the first (106) and second (108) devices to provide a clock signal, and the other wire is driven by either the first device (106) or the second device (108) depending which device is transmitting data. Accordingly, the two-wire interfaces (300) are operable in two modes (e.g. handshaking mode and data transfer mode) and one of the wires (302, 304) of the interface (300) may be driven by a different device in the two modes.

    Transition into and out of a partially-off power state
    7.
    发明授权
    Transition into and out of a partially-off power state 有权

    公开(公告)号：US12061510B2

    公开(公告)日：2024-08-13

    申请号：US17193222

    申请日：2021-03-05

    申请人： Advanced Micro Devices, Inc.

    发明人： Jyoti Raheja ,  Alexander J. Branover

    IPC分类号： G06F1/3206 ,  G06F1/3234 ,  G06F9/4401 ,  G06F9/54

    CPC分类号： G06F1/3206 ,  G06F1/3234 ,  G06F9/4401 ,  G06F9/542

    摘要： The computer system responds to a first trigger event to enter a partial off state in which a boot cycle is required to return to a working state. A device plugged into a serial bus port can be charged in the partial off state. A configuration register or runtime environment controls whether the computer system enters the partial off state in response to a trigger event. The computer system stays in the partial off state until another trigger event returns the computer system to the working state. In some implementations, the computer system leaves the partial off state and enters the shutdown state after an unplug event, a predetermined amount of time after an unplug event, a predetermined amount of time after entering the partial off state, a predetermined amount of time after charging of a device is complete, or any combination of such events.

    Network identification of portable electronic devices while changing power states
    8.
    发明授权
    Network identification of portable electronic devices while changing power states 有权

    公开(公告)号：US12032423B2

    公开(公告)日：2024-07-09

    申请号：US18190875

    申请日：2023-03-27

    申请人： Sonos, Inc.

    发明人： Hrishikesh Gossain

    IPC分类号： G06F1/32 ,  G06F1/3206 ,  G06F3/048 ,  H04L65/60 ,  H04N21/436 ,  H04N21/472

    CPC分类号： G06F1/3206 ,  G06F3/048 ,  H04L65/60 ,  H04N21/43615 ,  H04N21/47217

    摘要： Systems and methods for maintaining knowledge of a network address (e.g., a MAC address) for a playback device while changing power states are disclosed. In one embodiment, a method for maintaining knowledge of the network identity of a playback device while changing power states includes determining that a playback device is entering a sleep state, sending state information from the playback device to a central data repository over a network responsive to the determination that the playback device is entering sleep state, where state information includes a MAC address, receiving the state information about the playback device at a waking device from the central data repository, waking the playback device periodically at predetermined time intervals while in sleep state to listen for messages addressed to the MAC address, and receiving a wake-up message at the playback device from the waking device and responding by changing from sleep to active state.

    POWER AND THERMAL MANAGEMENT AND COORDINATED CONTROL OF AN INTEGRATED SYSTEM
    9.
    发明公开
    POWER AND THERMAL MANAGEMENT AND COORDINATED CONTROL OF AN INTEGRATED SYSTEM 审中-公开

    公开(公告)号：US20240218836A1

    公开(公告)日：2024-07-04

    申请号：US18089845

    申请日：2022-12-28

    申请人： General Electric Company

    发明人： Manxue Lu ,  James Ryan Reepmeyer ,  R. Sheldon Carpenter

    IPC分类号： F02C9/00 ,  B64D13/06 ,  G06F1/3206 ,  G06F1/329

    CPC分类号： F02C9/00 ,  B64D13/06 ,  G06F1/3206 ,  G06F1/329 ,  B64D2013/0618 ,  F05D2220/323 ,  F05D2260/81 ,  F05D2270/335 ,  F05D2270/44

    摘要： An integrated system and methods therefore are provided. An integrated system has individual power and/or thermal systems and a coordinated control system. The coordinated control system receives mission demands and priorities from an upstream system. The coordinated control system also receives a status and a prediction from each individual system, such as an individual system's operating mode status and its capability margin. The coordinated control system performs a conflict of interest check and generates a relative status for each individual system based on the status and predictions associated with the individual systems. The coordinated control system determines an operating mode and an allowed demand for each individual system based on the relative statuses and the mission demands and priorities. The coordinated control system outputs the operating modes to the individual systems and maps the allowed demands to individual system demands. The individual system demands are output to the individual systems.

    Domain clock and power activation control circuit to reduce voltage droop and related methods
    10.
    发明授权
    Domain clock and power activation control circuit to reduce voltage droop and related methods 有权

    公开(公告)号：US12019494B2

    公开(公告)日：2024-06-25

    申请号：US17853258

    申请日：2022-06-29

    申请人： Microsoft Technology Licensing, LLC

    发明人： Charles Boecker ,  Eric Groen ,  Shaishav A. Desai

    IPC分类号： G06F1/32 ,  G06F1/04 ,  G06F1/3206 ,  G06F1/3296

    CPC分类号： G06F1/3206 ,  G06F1/04 ,  G06F1/3296

    摘要： A domain control circuit includes a power regulator to supply power for a first domain on a power rail and a sequencing circuit to control the power regulator, and a clock gate signal to activate the domain. The sequencing circuit receives a domain control signal to control activation and deactivation of the domain. The domain control circuit deactivates the clock gate signal to the domain after controlling the power regulator to supply power for the domain on a power rail. In this manner, a voltage droop in a supply voltage on a power rail is reduced. In some examples, the clock gate signal to the domain is deactivated after a voltage increase on the power rail. In some examples, the power regulator includes a plurality of parallel regulator circuits and a regulator control circuit to determine a number of the parallel regulator circuits to be activated to power the domain.