公开(公告)号：US11551770B2

公开(公告)日：2023-01-10

申请号：US17244267

申请日：2021-04-29

申请人： SK hynix Inc.

发明人： Myung Ho Yang

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C17/16

摘要： An electronic device includes a row control circuit and a programming circuit. The row control circuit is suitable for activating a synthesis word line selection signal for enabling a first fuse cell and a second fuse cell in a first mode. In addition, the row control circuit is suitable for activating one of a first fuse access signal for storing fuse data in the first fuse cell or outputting the fuse data from the first fuse cell and a second fuse access signal for storing the fuse data in the second fuse cell or outputting the fuse data from the second fuse cell. The programming circuit is configured to store the fuse data in one of the first and second fuse cells based on the synthesis word line selection signal and the first and second fuse access signals in the first mode.

公开(公告)号：US11031407B2

公开(公告)日：2021-06-08

申请号：US16460266

申请日：2019-07-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Min-Shin Wu ,  Meng-Sheng Chang ,  Shao-Yu Chou ,  Yao-Jen Yang

IPC分类号： G11C17/00 ,  H01L27/112 ,  G11C17/18 ,  G11C17/16

摘要： An IC device includes an anti-fuse device including a dielectric layer between a first gate structure and an active area, a first transistor including a second gate structure overlying the active area, and a second transistor including a third gate structure overlying the active area. The first gate structure is between the second gate structure and the third gate structure.

公开(公告)号：US10991442B2

公开(公告)日：2021-04-27

申请号：US17013967

申请日：2020-09-08

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Der Chih ,  Chen-Ming Hung ,  Jen-Chou Tseng ,  Jam-Wem Lee ,  Ming-Hsiang Song ,  Shu-Chuan Lee ,  Shao-Yu Chou ,  Yu-Ti Su

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  H01L27/02 ,  G11C7/24

摘要： A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

公开(公告)号：US10957701B1

公开(公告)日：2021-03-23

申请号：US16679458

申请日：2019-11-11

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： HongLiang Shen ,  Meixiong Zhao ,  Guoxiang Ning

IPC分类号： G11C17/00 ,  H01L27/112 ,  G11C17/18 ,  G11C17/16 ,  H01L23/528

摘要： One IC product disclosed herein includes, among other things, a semiconductor substrate, a first anti-fuse device formed on the semiconductor substrate, the first anti-fuse device comprising at least one first fin formed with a first fin pitch, a first source region and a first drain region, wherein the first anti-fuse device is adapted to breakdown when a first programing voltage is applied to the first anti-fuse device, and a second anti-fuse device formed on the semiconductor substrate, the second anti-fuse device comprising at least one second fin formed with a second fin pitch, a second source region and a second drain region, wherein the second anti-fuse device is adapted to breakdown when a second programing voltage is applied to the second anti-fuse device, wherein the first fin pitch is greater than the second fin pitch and wherein the first programming voltage is greater than the second programing voltage.

公开(公告)号：US10884918B2

公开(公告)日：2021-01-05

申请号：US16260008

申请日：2019-01-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Chitra Subramanian ,  Seiji Munetoh ,  Ghavam Shahidi

IPC分类号： G11C17/00 ,  G06F12/02 ,  G11C17/14 ,  G06F9/38 ,  G06F9/54

摘要： A semiconductor structure includes a first processor on a first die of a substrate. There is a second processor on a second die of the substrate. There is a one-time programmable (OTP) memory programming circuit, outside of the first and second die, and shared by the first and second processors. Each of the first and second processors include a one-time programmable (OTP) memory. The OTP memory programming circuit is configured to program each OTP memory.

公开(公告)号：US10803967B2

公开(公告)日：2020-10-13

申请号：US16830429

申请日：2020-03-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yu-Der Chih ,  Chen-Ming Hung ,  Jen-Chou Tseng ,  Jam-Wem Lee ,  Ming-Hsiang Song ,  Shu-Chuan Lee ,  Shao-Yu Chou ,  Yu-Ti Su

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C7/24 ,  H01L27/02 ,  G11C17/16

摘要： A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.

公开(公告)号：US10176882B1

公开(公告)日：2019-01-08

申请号：US15636778

申请日：2017-06-29

申请人： Cisco Technology, Inc.

发明人： Tzachy Reinman ,  Tsion Shamay ,  Yair Fodor

IPC分类号： G11C17/00 ,  G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  G11C16/10 ,  G11C16/26 ,  G11C7/12

摘要： In one embodiment, an apparatus includes a non-volatile memory, a one-time programmable (OTP) memory, and a processor operative to write data values to the non-volatile memory and then initiate programming of a first bit of the OTP memory, the first bit being associated with locking the non-volatile memory from further data being written thereto, and after the non-volatile memory has been locked from further data being written thereto, initiate programming of the second bit of the OTP memory in order to lock the non-volatile memory from further data being erased therefrom.

公开(公告)号：US10032522B2

公开(公告)日：2018-07-24

申请号：US15620657

申请日：2017-06-12

申请人： Synopsys, Inc.

发明人： Harry Luan ,  Tao Su ,  Larry Wang ,  Charlie Cheng

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  H01L23/535 ,  H01L27/112 ,  G11C17/14

摘要： An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved.

公开(公告)号：US09793003B2

公开(公告)日：2017-10-17

申请号：US15265774

申请日：2016-09-14

申请人： Avalanche Technology, Inc.

发明人： Ebrahim Abedifard ,  Uday Chandrasekhar ,  Rajiv Yadav Ranjan ,  Yiming Huai

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  G11C11/16 ,  G11C7/20 ,  G11C11/00 ,  G11C17/02 ,  G11C7/04 ,  G11C29/52

CPC分类号： G11C17/18 ,  G11C7/04 ,  G11C7/20 ,  G11C11/005 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165 ,  G11C29/52

摘要： A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (MTJs) whose resistance is switchable; and a one-time-programmable (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed. Each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof. The second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.

公开(公告)号：US09754678B2

公开(公告)日：2017-09-05

申请号：US15099902

申请日：2016-04-15

申请人： Samsung Electronics Co., Ltd.

发明人： Do-Hoon Byun ,  Chang-Su Sim ,  Na-Rae Hong

IPC分类号： G11C17/00 ,  G11C17/18 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C17/16 ,  G11C29/027

摘要： A method of testing a semiconductor integrated circuit including a one-time programmable (OTP) memory device is provided. A program command is transferred from a tester to the OTP memory device. Programming and a programming verification are performed with respect to OTP memory cells in the OTP memory device in response to the program command. The OTP device generates accumulated verification result signal by accumulating program verification results with respect to the OTP memory cells. The accumulated verification result signal is transferred from the OTP memory device to the tester.