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公开(公告)号：US12101945B2
公开(公告)日：2024-09-24
申请号：US18225186
申请日：2023-07-24
发明人： Tomoaki Atsumi , Shuhei Nagatsuka , Tamae Moriwaka , Yuta Endo
IPC分类号： H10B69/00 , G11C7/16 , G11C8/14 , G11C11/24 , G11C11/403 , G11C11/408 , H01L27/06 , H01L29/24 , H01L29/786 , H10B41/20 , H10B41/70
CPC分类号： H10B69/00 , G11C7/16 , G11C8/14 , G11C11/24 , G11C11/403 , G11C11/4085 , H01L27/0688 , H01L29/24 , H01L29/7869 , H10B41/20 , H10B41/70
摘要： [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.-
公开(公告)号：US11929141B2
公开(公告)日：2024-03-12
申请号：US17643215
申请日：2021-12-08
发明人： Kaushik Roy , Amogh Agrawal , Mustafa Fayez Ahmed Ali , Indranil Chakraborty , Aayush Ankit , Utkarsh Saxena
CPC分类号： G11C7/16 , G11C7/1012 , G11C7/1063 , G11C7/109 , H03M1/1245
摘要： Sparsity-aware reconfiguration compute-in-memory (CIM) static random access memory (SRAM) systems are disclosed. In one aspect, a reconfigurable precision succession approximation register (SAR) analog-to-digital converter (ADC) that has the ability to form (n+m) bit precision using n-bit and m-bit sub-ADCs is provided. By controlling which sub-ADCs are used based on data sparsity, precision may be maintained as needed while providing a more energy efficient design.
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公开(公告)号：US11909413B2
公开(公告)日：2024-02-20
申请号：US17471887
申请日：2021-09-10
申请人： Kioxia Corporation
发明人： Atsushi Kawasumi
摘要： A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.
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公开(公告)号：US11881260B2
公开(公告)日：2024-01-23
申请号：US17538235
申请日：2021-11-30
发明人： Youngnam Hwang
CPC分类号： G11C13/004 , G11C7/16 , G11C11/54 , G11C13/0026 , G11C13/0069 , G11C2013/0054
摘要： A neuromorphic computing device includes first and second memory cell arrays, and an analog-to-digital converting circuit. The first memory cell array includes a plurality of resistive memory cells, generates a plurality of read currents based on a plurality of input signals and a plurality of data, and outputs the plurality of read currents through a plurality of bitlines or source lines. The second memory cell array includes a plurality of reference resistive memory cells and an offset resistor, and outputs a reference current through a reference bitline or a reference source line. The analog-to-digital converting circuit converts the plurality of read currents into a plurality of digital signals based on the reference current. The offset resistor is connected between the reference bitline and the reference source line.
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公开(公告)号：US20240021226A1
公开(公告)日：2024-01-18
申请号：US17863201
申请日：2022-07-12
发明人： Hung-Li Chiang , Jer-Fu Wang , Tzu-Chiang Chen , Meng-Fan Chang
CPC分类号： G11C7/16 , G11C7/1006 , G11C13/003 , G11C2213/77
摘要： In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.
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公开(公告)号：US20220366976A1
公开(公告)日：2022-11-17
申请号：US17538235
申请日：2021-11-30
发明人： Youngnam Hwang
摘要： A neuromorphic computing device includes first and second memory cell arrays, and an analog-to-digital converting circuit. The first memory cell array includes a plurality of resistive memory cells, generates a plurality of read currents based on a plurality of input signals and a plurality of data, and outputs the plurality of read currents through a plurality of bitlines or source lines. The second memory cell array includes a plurality of reference resistive memory cells and an offset resistor, and outputs a reference current through a reference bitline or a reference source line. The analog-to-digital converting circuit converts the plurality of read currents into a plurality of digital signals based on the reference current. The offset resistor is connected between the reference bitline and the reference source line.
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公开(公告)号：US20210343343A1
公开(公告)日：2021-11-04
申请号：US16864005
申请日：2020-04-30
摘要： In one embodiment, an electronic device includes a compute-in-memory (CIM) array that includes a plurality of columns. Each column includes a plurality of CIM cells connected to a corresponding read bitline, a plurality of offset cells configured to provide a programmable offset value for the column, and an analog-to-digital converter (ADC) having the corresponding bitline as a first input and configured to receive the programmable offset value. Each CIM cell is configured to store a corresponding weight.
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公开(公告)号：US11061766B2
公开(公告)日：2021-07-13
申请号：US16712358
申请日：2019-12-12
发明人： Ron M. Roth , Richard H. Henze
摘要： Examples disclosed herein relate to a fault-tolerant dot product engine. The fault-tolerant dot product engine has a crossbar array having a number l of row lines and a number n of column lines intersecting the row lines to form l×n memory locations, with each memory location having a programmable memristive element and defining a matrix value. A number l of digital-to-analog converters are coupled to the row lines of the crossbar array to receive an input signal and a number n of analog-to-digital converters are coupled to the column lines of the crossbar array to generate an output signal. The output signal is a dot product of the input signal and the matrix values in the crossbar array, wherein a number m
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公开(公告)号：US11049491B2
公开(公告)日：2021-06-29
申请号：US16828070
申请日：2020-03-24
摘要： Systems, methods, and computer-readable storage devices to improve the quality of synthetic speech generation. A system selects speech units from a speech unit database, the speech units corresponding to text to be converted to speech. The system identifies a desired prosodic curve of speech produced from the selected speech units, and also identifies an actual prosodic curve of the speech units. The selected speech units are modified such that a new prosodic curve of the modified speech units matches the desired prosodic curve. The system stores the modified speech units into the speech unit database for use in generating future speech, thereby increasing the prosodic coverage of the database with the expectation of improving the output quality.
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公开(公告)号：US10964393B2
公开(公告)日：2021-03-30
申请号：US16521784
申请日：2019-07-25
发明人： Hikaru Tamura
摘要： Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.
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