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    Magnetic Memory Element Including Perpendicular Enhancement Layer and Oxide Cap Layer
    1.
    发明申请
    Magnetic Memory Element Including Perpendicular Enhancement Layer and Oxide Cap Layer 有权

    公开(公告)号：US20250063952A1

    公开(公告)日：2025-02-20

    申请号：US18927997

    申请日：2024-10-26

    Applicant: Avalanche Technology, Inc.

    Inventor： Zihui Wang ,  Yiming Huai

    IPC: H10N50/10 ,  B82Y40/00 ,  G11C11/15 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L29/66 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

    Abstract: A magnetic memory element including first and second magnetic free layers having a variable magnetization direction substantially perpendicular to layer planes thereof; a first perpendicular enhancement layer (PEL) interposed between the first and second magnetic free layers; first and second magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof; a second PEL interposed between the first and second magnetic reference layers; an insulating tunnel junction layer formed between the first magnetic free layer and reference layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer and having a second invariable magnetization direction substantially opposite to the first invariable magnetization direction; and a cap layer formed adjacent to the second magnetic free layer and comprising iron, oxygen, and a metal element.

    MAGNETIC MEMORY DEVICE
    5.
    发明申请
    MAGNETIC MEMORY DEVICE 有权

    公开(公告)号：US20250029644A1

    公开(公告)日：2025-01-23

    申请号：US18773949

    申请日：2024-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Unghwan Pi ,  Stuart Papworth Parkin ,  Jaechun Jeon ,  Jaekeun Kim ,  Andrea Migliorini

    IPC: G11C11/16 ,  G11C11/18 ,  G11C19/08 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

    Abstract: A magnetic memory device includes a lower magnetic track layer extending in a first direction and including a plurality of first magnetic domains, a spacer layer on the lower magnetic track layer and extending in the first direction, an upper magnetic track layer on the spacer layer and extending in the first direction, the upper magnetic track layer including a plurality of second magnetic domains, and a plurality of read units on the upper magnetic track layer and arranged apart from one another in the first direction, wherein the plurality of first magnetic domains and the plurality of second magnetic domains have magnetization directions parallel to each other at positions overlapping each other in a second direction perpendicular to the first direction.

    SEMICONDUCTOR DEVICE INCLUDING MAGNETIC TUNNEL JUNCTION STRUCTURE
    6.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING MAGNETIC TUNNEL JUNCTION STRUCTURE 有权

    公开(公告)号：US20250008843A1

    公开(公告)日：2025-01-02

    申请号：US18538378

    申请日：2023-12-13

    Applicant: SK hynix Inc.

    Inventor： Soo Man SEO

    IPC: H10N50/20 ,  H01F10/32 ,  H10B61/00

    Abstract: In an embodiment, a semiconductor device includes a spin orbit torque (SOT) line extending in a first direction; an electrode layer spaced apart from the SOT line in a third direction; and a magnetic tunnel junction structure interposed between the SOT line and the electrode layer, and including a free layer adjacent to the SOT line in the third direction, a pinned layer adjacent to the electrode layer in the third direction, and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein the magnetic tunnel junction structure includes a first portion overlapping the SOT line and a second portion not overlapping the SOT line in a second direction, the electrode layer overlaps at least a portion of the second portion, and a thickness of the free layer in the first portion is greater than a thickness of the free layer in the second portion.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20240431214A1

    公开(公告)日：2024-12-26

    申请号：US18224050

    申请日：2023-07-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hui-Lin Wang

    IPC: H10N50/01 ,  H01F10/32 ,  H10N50/85

    Abstract: A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric (IMD) layer on a substrate, forming a contact hole in the IMD layer, forming a barrier layer and a metal layer in the contact hole, planarizing the metal layer, forming a spin orbit torque (SOT) layer on the barrier layer and the metal layer, and then forming a magnetic tunneling junction (MTJ) on the SOT layer.

    MAGNETORESISTANCE ELEMENT INCLUDING A SKYRMION LAYER AND A VORTEX LAYER THAT ARE MAGNETICALLY COUPLED TO EACH OTHER
    8.
    发明申请
    MAGNETORESISTANCE ELEMENT INCLUDING A SKYRMION LAYER AND A VORTEX LAYER THAT ARE MAGNETICALLY COUPLED TO EACH OTHER 有权

    公开(公告)号：US20240420878A1

    公开(公告)日：2024-12-19

    申请号：US18333680

    申请日：2023-06-13

    Applicant: Allegro MicroSystems, LLC

    Inventor： Samridh JAISWAL

    IPC: H01F10/32 ,  G01R33/09

    Abstract: According to one aspect of the present disclosure, a magnetoresistance (MR) element includes a free layer. In some embodiments, the free layer also includes a vortex layer comprising a vortex and a skyrmion layer magnetically coupled to the vortex layer. In some embodiments, in the skyrmion layer is configured to form skyrmions that reduce annihilation of the vortex thereby increasing a linear response range of the MR element. In some embodiments, the MR element is a tunneling magnetoresistance element or a giant magnetoresistance element. In some embodiments, the MR element includes a barrier layer, wherein the vortex layer is closer to the barrier layer than the skyrmion layer.

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