公开(公告)号：US20250038126A1

公开(公告)日：2025-01-30

申请号：US18784941

申请日：2024-07-26

Applicant: MEDIATEK INC.

Inventor： De-Wei Liu ,  Pu-Shan Huang ,  Sang-Mao Chiu ,  Shih-Yi Syu

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/055 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/58

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface, and a vertical sidewall extending between the top surface and the bottom surface; an integrated circuit die mounted within a device region on the top surface of the substrate; a metal interconnect structure embedded within the device region of the substrate, wherein the integrated circuit die is electrically connected to the metal interconnect structure; and a peripheral shielding ring embedded within a peripheral region of the substrate. The peripheral region surrounds the device region. A lid is mounted on the top surface of the substrate. The lid is electrically connected with the peripheral shielding ring.

公开(公告)号：US20240194544A1

公开(公告)日：2024-06-13

申请号：US18581213

申请日：2024-02-19

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Sang Jae Jang ,  Weilung Lu ,  Burt Barber ,  Adrian Arcedera ,  Shingo Nakamura

IPC: H01L23/043 ,  H01L21/50 ,  H01L21/52 ,  H01L23/04 ,  H01L23/055 ,  H01L23/06 ,  H01L23/10 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/043 ,  H01L21/50 ,  H01L21/52 ,  H01L23/04 ,  H01L23/055 ,  H01L23/06 ,  H01L23/10 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49838

Abstract: In one example, a semiconductor device comprises a substrate comprising a top side, a bottom side, and a conductive structure, a body over the top side of the substrate, an electronic component over the top side of the substrate and adjacent to the body, wherein the electronic component comprises an interface element on a top side of the electronic component, a lid over the interface element and a seal between the top side of the electronic component and the lid, and a buffer on the top side of the substrate between the electronic component and the body. Other examples and related methods are also disclosed herein.

公开(公告)号：US11984390B2

公开(公告)日：2024-05-14

申请号：US17222809

申请日：2021-04-05

Applicant: Hamilton Sundstrand Corporation

Inventor： Eileen A. Bartley

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/055 ,  H05K3/34

CPC classification number: H01L23/49816 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/06 ,  H01L23/055 ,  H01L2924/15311 ,  H05K3/3436

Abstract: A ball grid array (BGA) assembly can include a component substrate having at least one underfill channel defined therethrough providing fluidic communication between a first side of the component substrate and a second side of the component substrate, a plurality of pads or leads exposed on the second side and configured to be soldered to a mating PCB, a cover mounted to the component substrate defining a reservoir cavity between the first side and the cover, and an underfill material disposed within the reservoir cavity such that the underfill material can flow through the at least one underfill channel to a gap defined between the second side and the mating PCB when the component substrate is being soldered to the mating PCB.

公开(公告)号：US20230420430A1

公开(公告)日：2023-12-28

申请号：US17848500

申请日：2022-06-24

Applicant: Wolfspeed, Inc.

Inventor： Qianli Mu ,  Michael DeVita ,  Alexander Komposch ,  Basim Noori

IPC: H01L25/16 ,  H01L23/055 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L25/165 ,  H01L23/055 ,  H01L23/367 ,  H01L23/49822

Abstract: A transistor device package includes a transistor die comprising a gate terminal, a drain terminal, and a source terminal, and a passive component assembly including the transistor die on a surface thereof and comprising one or more passive electrical components electrically coupled to the gate terminal, the drain terminal, and/or the source terminal. A mold structure may be provided on the one or more passive electrical components. One or more conductive pads may be exposed by the mold structure. A support structure may extend along one or more sides of the transistor die on the surface of the passive component assembly. The support structure may provide a cavity that extends around the transistor die, and/or may be thermally conductive. Related devices and component assemblies are also discussed.

公开(公告)号：US11815749B2

公开(公告)日：2023-11-14

申请号：US16087985

申请日：2017-03-27

Applicant: KYOCERA Corporation

Inventor： Hiroyuki Nakamichi ,  Takayuki Shirasaki

IPC: G02F1/03 ,  H01L23/055 ,  H05K1/18 ,  G02F1/055

CPC classification number: G02F1/0305 ,  H01L23/055 ,  H05K1/18 ,  H05K1/189 ,  G02F1/055 ,  H05K2201/10121

Abstract: A functional element housing package includes a pin terminal disposed in an outer region of a housing for housing a functional element. A wiring substrate is connected with the pin terminal. The wiring substrate includes a through hole for receiving the pin terminal, a first metallic layer disposed around an opening of the through hole on a side of the wiring substrate which side is located close to the housing, a second metallic layer disposed around an opening of the through hole on a side of the wiring substrate which is opposed to the side located close to the housing, the second metallic layer being greater in area than the first metallic layer, a connection wiring line connected to the first metallic layer or the second metallic layer, and a solder which connects the pin terminal to each of the first metallic layer and the second metallic layer.

公开(公告)号：US20230063689A1

公开(公告)日：2023-03-02

申请号：US18047861

申请日：2022-10-19

Applicant: Medtronic MiniMed, Inc.

Inventor： Daniel Hahn ,  David L. Probst ,  Randal C. Schulhauser ,  Mohsen Askarinya ,  Patrick W. Kinzie ,  Thomas P. Miltich ,  Mark D. Breyen ,  Santhisagar Vaddiraju

IPC: A61B5/00 ,  H01L21/48 ,  H01L21/52 ,  H01L21/78 ,  H01L23/055 ,  H01L23/498 ,  H01L23/66 ,  A61B5/145 ,  A61B5/1468

Abstract: An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack.

公开(公告)号：US20230018343A1

公开(公告)日：2023-01-19

申请号：US17748335

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yu-Sheng LIN ,  Shu-Shen Yeh ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chien Hung Chen ,  Chia-Kuei Hsu

IPC: H01L23/055 ,  H01L25/065 ,  H01L23/10 ,  H01L21/48

Abstract: A package assembly includes a package substrate, a package lid located on the package substrate and including a plate portion, an outer foot extending from the plate portion, and an inner foot having a height greater than or equal to a height of the outer foot, extending from the plate portion and including a first inner foot corner portion located inside a first corner of the outer foot, and an adhesive that adheres the outer foot to the package substrate and adheres the inner foot to the package substrate.

公开(公告)号：US11417631B2

公开(公告)日：2022-08-16

申请号：US16522112

申请日：2019-07-25

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yun Tae Lee ,  Hyung Joon Kim ,  Han Kim

IPC: H01L25/065 ,  H01L23/055 ,  H01L23/13 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16

Abstract: A semiconductor package includes: a first semiconductor package including: a first frame having a first through portion, a first semiconductor chip in the first through portion and having a first surface on which a first connection pad is disposed and a second surface on which a second connection pad is disposed, and a through via connected to the second connection pad, a first connection structure on the first surface and including a first redistribution layer, and a backside redistribution layer on the second surface; and a second semiconductor package on the first semiconductor package and including: a second connection structure including a second redistribution layer, a second frame on the second connection structure and having a second through portion, and a second semiconductor chip in a second through portion and having a third surface on which a third connection pad is disposed.

公开(公告)号：US11348851B2

公开(公告)日：2022-05-31

申请号：US17106636

申请日：2020-11-30

Applicant: Mitsubishi Electric Corporation

Inventor： Yasutaka Shimizu

IPC: H01L23/48 ,  H01L23/34 ,  H01L21/00 ,  H05K7/00 ,  H05K5/00 ,  H01L23/049 ,  H01L23/10 ,  H01L23/367 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/373 ,  H01L23/055 ,  H01L23/053 ,  B23K3/047

Abstract: An object is to provide a technology for enabling reduction in the time and cost taken to manufacture a die to be used for molding a case that surrounds semiconductor elements. A semiconductor device includes a base plate, a cooling plate, an insulating substrate, a semiconductor element, a case, a lead frame formed integrally with the case and including a terminal formed on one end portion of the lead frame and protruding outward, and a sealant. The case includes a pair of first case components arranged to face each other, and a pair of second case components arranged to face each other and crossing the pair of first case components. Joining end portions of the first case components to end portions of the pair of second case components forms the case.

公开(公告)号：US20220059427A1

公开(公告)日：2022-02-24

申请号：US17370953

申请日：2021-07-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Kenji SASAKI ,  Shigeki KOYA

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L23/42 ,  H01L23/31 ,  H01L23/055 ,  H01L25/18 ,  H05K1/18 ,  H05K1/11

Abstract: A semiconductor package includes a module substrate having opposite top and bottom surfaces, a semiconductor chip provided with bumps and mounted on the top surface of the module substrate via the bumps, and a metal member having a top portion disposed at a level higher than the semiconductor chip with reference to the top surface of the module substrate and including the semiconductor chip in plan view and a side portion extending from the top portion toward the module substrate. The module substrate includes a first metal film disposed on or in at least one of the bottom surface and an internal layer of the module substrate. The first metal film is electrically connected to the bumps and reaches a side surface of the module substrate. The side portion is thermally coupled to the first metal film at the side surface of the module substrate.