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公开(公告)号：US20240136806A1
公开(公告)日：2024-04-25
申请号：US18465173
申请日：2023-09-11
IPC分类号： H02H3/027 , H03K17/284
CPC分类号： H02H3/027 , H03K17/284
摘要： An automatic power off circuit of a non-rebound switch includes: a power switch circuit, the non-rebound switch, a trigger circuit, a controller, and a power on-off control circuit; the trigger circuit is connected with the power switch circuit and the non-rebound switch, and configured to send a turn-on signal to the power switch circuit to turn on the power switch circuit when the non-rebound switch is turned on; the controller is connected with the power switch circuit and configured to detect continuous turn-on time of the non-rebound switch and output a turn-off signal in response to the continuous turn-on time exceeding a preset timing time; the power on-off control circuit is connected with the controller, the power switch circuit and the non-rebound switch, and configured to turn off the power switch circuit by using the turn-off signal. A problem that non-rebound switches cannot be automatically powered off can be solved.
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公开(公告)号：US11901889B2
公开(公告)日：2024-02-13
申请号：US17898557
申请日：2022-08-30
申请人： DENSO CORPORATION
发明人： Hironori Akiyama , Tetsuya Dewa
IPC分类号： H02M1/08 , H03K17/16 , H03K17/687 , H03K17/284
CPC分类号： H03K17/687 , H02M1/08 , H03K17/16 , H03K17/284
摘要： A gate drive device drives a gate of a semiconductor switching element constituting an upper or lower arm of a half bridge circuit which supplies an output current, which is alternating current, to a load. The gate drive device detects a peak value of an element voltage which is a voltage of a main terminal of the semiconductor switching element or a change rate of the element voltage when the semiconductor switching element is switching. The gate drive device acquires a maximum value among a plurality of peak values or a plurality of change rates during a predetermined detection period including a period in which the semiconductor switching element performs switching multiple number of times.
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公开(公告)号：US11621709B2
公开(公告)日：2023-04-04
申请号：US17211563
申请日：2021-03-24
发明人： Ryu Araki
IPC分类号： H03K17/284 , H02M7/5387 , H02M1/38 , H03K5/1534 , H02P27/06 , H03K5/24 , G01R19/165 , H02P6/28 , H03K5/00 , H02M1/00
摘要： A power module, including a high-side switching element and a low-side switching element connected to form a half bridge circuit, a high-side drive circuit which drives the high-side switching element, a low-side drive circuit which drives the low-side switching element, and a high-side current detection circuit which detects a current of the high-side switching element. The high-side drive circuit includes a high-side variable delay circuit which adjusts, according to a value detected by the high-side current detection circuit, a length of a high-side delay time from a time when a signal is inputted to the high-side drive circuit to a time when the high-side switching element is driven.
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公开(公告)号：US11601125B2
公开(公告)日：2023-03-07
申请号：US17303792
申请日：2021-06-08
IPC分类号： H03K17/687 , H03K17/041 , H03K17/284
摘要： The present description concerns a method of controlling at least one switch (TH), including: the reception of signals (S3-i) having between one another at least one phase shift representative of a desired state of said at least one switch; the obtaining, from said signals, of a value (Si) representative of the desired state; and the application of the representative value to said at least one switch.
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公开(公告)号：US11264983B1
公开(公告)日：2022-03-01
申请号：US17087262
申请日：2020-11-02
发明人： Cetin Kaya , Nathan Richard Schemm
IPC分类号： H03K17/16 , H03K17/30 , H03K17/284
摘要： Methods, apparatus, systems and articles of manufacture are described to parallelize transistors. An example apparatus includes a first transistor on a first die and a second transistor on a second die. The example apparatus includes a parallel feedback terminal coupled to the first die and the second die and a current sensor including a first contact and a second contact. The example apparatus includes a resistor coupled to the current sensor and at least one of the switched terminal or a ground terminal. The example apparatus includes an active drive controller including a first input coupled to the resistor, a second input coupled to the parallel feedback terminal, and an output coupled to the parallel feedback terminal. The example apparatus includes an edge delay controller adapted to be coupled to a gate driver and an error amplifier, and a control contact adapted to be coupled to the gate driver.
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公开(公告)号：US11264903B2
公开(公告)日：2022-03-01
申请号：US15707257
申请日：2017-09-18
发明人： Pei-Hsin Liu , James Michael Walden
摘要： A power converter circuit includes a power stage that includes a transformer and a switch. The switch can be controlled in response to a PWM signal to provide a primary current through a primary winding of the transformer to induce a secondary current in a secondary winding of the transformer to generate an output voltage. The power stage includes a switching node between the switch and the primary winding having a switching voltage. The circuit also includes a switching controller configured to generate the PWM signal in response to a ramp signal. The ramp signal can have an amplitude of a slope that is proportional to a decay rate of a magnetizing current of the transformer and generated in response to feedback from the power stage. The switch can be activated in response to the switching voltage having an amplitude of approximately zero volts based on the amplitude of the ramp signal.
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公开(公告)号：US11258446B2
公开(公告)日：2022-02-22
申请号：US16862071
申请日：2020-04-29
申请人： Apple Inc.
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08 , H03K19/094 , H03K17/284 , G06F1/10
摘要： Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.
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公开(公告)号：US11196414B2
公开(公告)日：2021-12-07
申请号：US16921790
申请日：2020-07-06
申请人： pSemi Corporation
IPC分类号： H03K17/16 , H03K17/10 , H03K17/284 , H03K17/687 , H03K17/689 , H03K17/04 , H03K17/06 , H03K17/08
摘要： A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.
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公开(公告)号：US20210359676A1
公开(公告)日：2021-11-18
申请号：US17211563
申请日：2021-03-24
发明人： Ryu ARAKI
IPC分类号： H03K17/284 , H02M7/5387 , H02M1/38 , H03K5/1534 , H02P6/28 , H02P27/06 , H03K5/24 , G01R19/165
摘要： A power module, including a high-side switching element and a low-side switching element connected to form a half bridge circuit, a high-side drive circuit which drives the high-side switching element, a low-side drive circuit which drives the low-side switching element, and a high-side current detection circuit which detects a current of the high-side switching element. The high-side drive circuit includes a high-side variable delay circuit which adjusts, according to a value detected by the high-side current detection circuit, a length of a high-side delay time from a time when a signal is inputted to the high-side drive circuit to a time when the high-side switching element is driven.
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公开(公告)号：US20210351688A1
公开(公告)日：2021-11-11
申请号：US17380135
申请日：2021-07-20
摘要： A circuit includes a first gate control circuit including a first time delay element and first and second logic gates. The first time delay element and first and second logic gates receive a pulse width modulation (PWM) signal. The first logic gate includes a first output and second logic gate includes a second output. The circuit also includes a second gate control circuit that includes a second time delay element and third and fourth logic gates. The second time delay element includes an input coupled to the output of the first time delay element. The third logic gate includes a third output, and the fourth logic gate includes a fourth output. A first gate driver receives a first signal from one of the first or third outputs. A second gate driver receives a second signal from one of the second or fourth outputs.
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