公开(公告)号：WO2014092775A1

公开(公告)日：2014-06-19

申请号：PCT/US2013/045913

申请日：2013-06-14

Applicant: INTEL CORPORATION ,  MANIPATRUNI, Sasikanth ,  DOYLE, Brian, S. ,  LIFF, Shawna, M. ,  SINGH, Vivek, K.

Inventor： MANIPATRUNI, Sasikanth ,  DOYLE, Brian, S. ,  LIFF, Shawna, M. ,  SINGH, Vivek, K.

IPC: D02G3/36 ,  D03D15/00 ,  D04H1/42 ,  D01D5/34

CPC classification number: D03D1/0088 ,  B21C23/08 ,  B21C37/042 ,  B21C37/047 ,  D01D5/00 ,  D01D5/34 ,  D02G3/441 ,  D04H1/4266 ,  D04H1/4382 ,  D04H3/00 ,  D10B2401/16 ,  D10B2401/18 ,  Y10T442/3057 ,  Y10T442/603

Abstract: Flexible electronically functional fibers are described that allow for the placement of electronic functionality in traditional fabrics. The fibers can be interwoven with natural fibers to produce electrically functional fabrics and devices that can retain their original appearance.

Abstract translation: 描述了允许在传统织物中放置电子功能的柔性电子功能纤维。 纤维可与天然纤维交织以产生可保持其原始外观的电功能织物和装置。

公开(公告)号：WO2007011394A3

公开(公告)日：2007-01-25

申请号：PCT/US2005/037379

申请日：2005-10-18

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY ,  KUMAR, Nitin ,  LIFF, Shawna, M. ,  MCKINLEY, Gareth, H.

Inventor： KUMAR, Nitin ,  LIFF, Shawna, M. ,  MCKINLEY, Gareth, H.

IPC: C08K3/34 ,  C08K9/02 ,  C08K9/04

Abstract: A method of dispersing particles in a medium. The method includes providing a first particle/solvent dispersion comprising the particles and a first solvent, adding a second solvent to the first particle/solvent dispersion to form a second particle/solvent dispersion, wherein the first solvent and the second solvent are miscible, and extracting substantially all of the first solvent from the second particle/solvent dispersion to form a third particle/solvent dispersion.

公开(公告)号：WO2019133008A1

公开(公告)日：2019-07-04

申请号：PCT/US2017/069138

申请日：2017-12-30

Applicant: INTEL CORPORATION ,  MALLIK, Debendra ,  SANKMAN, Robert L. ,  NICKERSON, Robert ,  MODI, Mitul ,  GANESAN, Sanka ,  SWAMINATHAN, Rajasekaran ,  KARHADE, Omkar ,  LIFF, Shawna M. ,  ALUR, Amruthavalli ,  CHAVALI, Sri Chaitra J.

Inventor： MALLIK, Debendra ,  SANKMAN, Robert L. ,  NICKERSON, Robert ,  MODI, Mitul ,  GANESAN, Sanka ,  SWAMINATHAN, Rajasekaran ,  KARHADE, Omkar ,  LIFF, Shawna M. ,  ALUR, Amruthavalli ,  CHAVALI, Sri Chaitra J.

IPC: H01L25/07 ,  H01L23/538 ,  H01L23/498 ,  H01L23/28 ,  H01L23/00

Abstract: Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 µm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

公开(公告)号：WO2018063367A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054900

申请日：2016-09-30

Applicant: INTEL CORPORATION ,  KAMGAING, Telesphor ,  OSTER, Sasha ,  DOGIAMIS, Georgios ,  ELSHERBINI, Adel ,  LIFF, Shawna ,  ALEKSOV, Aleksandar ,  SWAN, Johanna ,  RAWLINGS, Brandon

Inventor： KAMGAING, Telesphor ,  OSTER, Sasha ,  DOGIAMIS, Georgios ,  ELSHERBINI, Adel ,  LIFF, Shawna ,  ALEKSOV, Aleksandar ,  SWAN, Johanna ,  RAWLINGS, Brandon

IPC: H01P1/04 ,  H01P3/12 ,  H01P5/08

CPC classification number: H01P1/042 ,  H01P1/022 ,  H01P3/12 ,  H01P3/121 ,  H01P3/122 ,  H01P11/002

Abstract: Generally, this disclosure provides apparatus and systems for coupling waveguides to a server package with a modular connector system, as well as methods for fabricating such a connector system. Such a system may be formed with connecting waveguides that turn a desired amount, which in turn may allow a server package to send a signal through a waveguide bundle in any given direction without bending waveguides.

Abstract translation: 通常，本公开提供了用于将波导耦合到具有模块化连接器系统的服务器封装的装置和系统，以及用于制造这种连接器系统的方法。 这种系统可以用连接波导形成，该连接波导转动所需量，这又可以允许服务器封装在任何给定方向上通过波导束发送信号而不弯曲波导。

公开(公告)号：WO2018063351A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054856

申请日：2016-09-30

Applicant: ELSHERBINI, Adel A. ,  SWAN, Johanna M. ,  LIFF, Shawna M. ,  BRAUNISCH, Henning ,  BHARATH, Krishna ,  SOTO GONZALEZ, Javier ,  FALCON, Javier A.

Inventor： ELSHERBINI, Adel A. ,  SWAN, Johanna M. ,  LIFF, Shawna M. ,  BRAUNISCH, Henning ,  BHARATH, Krishna ,  SOTO GONZALEZ, Javier ,  FALCON, Javier A.

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

Abstract translation: 所公开的各种实施例涉及一种半导体封装。 本发明的半导体封装包括衬底。 衬底由交替的导电层和电介质层形成。 第一有源电子部件设置在基板的外表面上，并且第二有源电子部件至少部分地嵌入在基板内。 第一互连区域由第一有源电子部件和第二有源电子部件之间的多个互连形成。 在第一有源电子元件和衬底之间，第二互连区域由多个互连形成。 另外，第三互连区域由第二有源电子部件和衬底之间的多个互连形成。

公开(公告)号：WO2018063198A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054240

申请日：2016-09-28

Applicant: ALEKSOV, Aleksandar ,  NGUYEN, Son V. ,  GOYAL, Rajat ,  LAMPNER, David B. ,  SENEVIRATNE, Dilan ,  LOPEZ, Albert S. ,  HEPPNER, Joshua D. ,  PIETAMBARAM, Srinivas V. ,  LIFF, Shawna M. ,  DABBY, Nadine L.

Inventor： ALEKSOV, Aleksandar ,  NGUYEN, Son V. ,  GOYAL, Rajat ,  LAMPNER, David B. ,  SENEVIRATNE, Dilan ,  LOPEZ, Albert S. ,  HEPPNER, Joshua D. ,  PIETAMBARAM, Srinivas V. ,  LIFF, Shawna M. ,  DABBY, Nadine L.

IPC: G04G17/04 ,  G04B37/14 ,  A44C5/00 ,  G06F1/16

Abstract: The document discloses a stretchable packaging system for a wearable electronic device. The system includes a first electronic component and a flexible trace connected to the first electronic component. An elastomer layer having a variable thickness at least partially encapsulates the first electronic component and the flexible trace. A first region of the layer has a first thickness that is greater than a second thickness of a second region of the layer that at least partially encapsulates the trace.

Abstract translation: 该文献公开了用于可穿戴电子设备的可拉伸包装系统。 该系统包括第一电子部件和连接到第一电子部件的柔性迹线。 具有可变厚度的弹性体层至少部分地封装第一电子部件和柔性迹线。 该层的第一区域具有第一厚度，该第一厚度大于至少部分地封装迹线的层的第二区域的第二厚度。

公开(公告)号：WO2013101184A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068105

申请日：2011-12-30

Applicant: INTEL CORPORATION ,  KOBRINSKY, Mauro J. ,  BRAUNISCH, Henning ,  LIFF, Shawna M. ,  CHANG, Peter L. ,  BLOCK, Bruce A. ,  SWAN, Johanna M.

Inventor： KOBRINSKY, Mauro J. ,  BRAUNISCH, Henning ,  LIFF, Shawna M. ,  CHANG, Peter L. ,  BLOCK, Bruce A. ,  SWAN, Johanna M.

IPC: G02B6/12 ,  G02B6/24

CPC classification number: G02B6/12004 ,  G02B6/12 ,  G02B6/30 ,  G02B6/4214 ,  G02B6/4257 ,  G02B6/428 ,  G02B2006/12061 ,  G02B2006/12121 ,  G02B2006/12123 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/167 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83048 ,  H01L2224/83102 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/15311 ,  H01L2924/15312 ,  H04B10/25 ,  H04B10/40 ,  H04B10/801 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Photonic components are placed on the processor package to bring the optical signal close to the processor die. The processor package includes a substrate to which the processor die is coupled, and which allows the processor die to connect to a printed circuit board. The processor package also includes transceiver logic, electrical-optical conversion circuits, and an optical coupler. The electrical-optical conversion circuits can include laser(s), modulator(s), and photodetector(s) to transmit and receive and optical signal. The coupler interfaces to a fiber that extends off the processor package. Multiple fibers can be brought to the processor package allowing for a scalable high-speed, high-bandwidth interconnection to the processor.

Abstract translation: 光子元件放置在处理器封装上，使光信号靠近处理器管芯。 处理器封装包括处理器管芯耦合到其上的基板，并且允许处理器管芯连接到印刷电路板。 处理器封装还包括收发器逻辑，电光转换电路和光耦合器。 电光转换电路可以包括激光器，调制器和用于发射和接收光信号的光电检测器。 耦合器连接到从处理器封装延伸的光纤。 多个光纤可以被带到处理器封装，允许与处理器的可扩展的高速，高带宽互连。

公开(公告)号：WO2012129153A3

公开(公告)日：2012-12-27

申请号：PCT/US2012029617

申请日：2012-03-19

Applicant: INTEL CORP ,  HU CHUAN ,  LIFF SHAWNA M ,  CLEMONS GREGORY S

Inventor： HU CHUAN ,  LIFF SHAWNA M ,  CLEMONS GREGORY S

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81805

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Abstract translation: 本公开涉及制造微电子封装的领域，其中空腔被形成在沉积在第一衬底上的电介质层中以维持焊接互连之间的分隔。 在一个实施例中，空腔可以具有倾斜的侧壁。 在另一个实施例中，焊膏可以沉积在空腔中并且在加热时可以形成焊料结构。 在其他实施例中，焊料结构可以放置在空腔中或者可以形成在第一衬底可以连接到的第二衬底上。 在其他实施例中，可以在第一基板和第二基板两者上形成焊料结构。 焊料结构可以用于通过与第二衬底上的接触区或焊料结构接触和回流来形成焊料互连。

公开(公告)号：WO2019066988A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054672

申请日：2017-09-30

Applicant: INTEL CORPORATION ,  LIFF, Shawna M. ,  ELSHERBINI, Adel A. ,  FALCON, Javier A. ,  MYERS, Preston T. ,  SAUCEDO, Joe R. ,  LOPEZ, Albert S. ,  SWAN, Johanna M.

Inventor： LIFF, Shawna M. ,  ELSHERBINI, Adel A. ,  FALCON, Javier A. ,  MYERS, Preston T. ,  SAUCEDO, Joe R. ,  LOPEZ, Albert S. ,  SWAN, Johanna M.

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/12 ,  H01L23/00

Abstract: Embodiments of a device package and a method of forming the device package are described. The device package has a substrate having a cavity and pads on at least one of a top and bottom surface, and a first die embedded in the cavity of the substrate. The device package includes a second die having an adhesive layer on a bottom surface of the second die, where the second die and the adhesive layer are disposed on the first die and substrate. The device package includes dies disposed on the second die and on top of one another to form a stack, wherein each die has die contacts on at least one of a top and bottom surface, where at least one of the die contacts of each die is electrically coupled to at least one of the die contacts of another die and pads of the substrate with interconnects.

公开(公告)号：WO2019066987A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/054671

申请日：2017-09-30

Applicant: INTEL CORPORATION ,  FALCON, Javier A. ,  LIFF, Shawna M. ,  MYERS, Preston T. ,  LOPEZ, Albert S. ,  SAUCEDO, Joe R. ,  ELSHERBINI, Adel A. ,  SWAN, Johanna M.

Inventor： FALCON, Javier A. ,  LIFF, Shawna M. ,  MYERS, Preston T. ,  LOPEZ, Albert S. ,  SAUCEDO, Joe R. ,  ELSHERBINI, Adel A. ,  SWAN, Johanna M.

IPC: H01L25/065 ,  H01L25/07 ,  H01L23/495

Abstract: A method of forming a package layer includes disposing dies in a cavity of a dam formed on the adhesive layer, forming a first encapsulation layer around the dies in the cavity of the dam, wherein the first encapsulation layer is formed below the top surfaces of first dies, and disposing second dies on the top surfaces of the first dies. The method further includes forming a second encapsulation layer around the second dies, the interconnects, and on a top surface of the first encapsulation layer in the cavity, wherein the second encapsulation layer is formed below the top surfaces of the topmost dies of the second dies, disposes third dies on the top surfaces of the topmost dies of the second dies, and forming a third encapsulation layer over and around the third dies, the remaining interconnects, and a top surface of the second encapsulation layer in the cavity.