公开(公告)号：WO2012129153A2

公开(公告)日：2012-09-27

申请号：PCT/US2012/029617

申请日：2012-03-19

Applicant: INTEL CORPORATION ,  HU, Chuan ,  LIFF, Shawna M. ,  CLEMONS, Gregory S.

Inventor： HU, Chuan ,  LIFF, Shawna M. ,  CLEMONS, Gregory S.

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H05K1/181 ,  H01L2924/01083 ,  H01L2924/00014

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Abstract translation: 本公开涉及制造微电子封装的领域，其中在沉积在第一基板上的电介质层中形成空腔以保持焊接互连之间的分离。 在一个实施例中，空腔可以具有倾斜的侧壁。 在另一个实施例中，焊膏可以沉积在空腔中，并且在加热时可以形成焊料结构。 在其它实施例中，焊料结构可以放置在空腔中，或者可以形成在可以连接第一衬底的第二衬底上。 在其它实施例中，可以在第一基板和第二基板上形成焊料结构。 焊料结构可以用于通过与第二衬底上的接触焊盘或焊料结构的接触和回流来形成焊料互连。

公开(公告)号：WO2015183264A1

公开(公告)日：2015-12-03

申请号：PCT/US2014/039834

申请日：2014-05-28

Applicant: INTEL CORPORATION ,  HU, Chuan ,  ELSHERBINI, Adel A. ,  TOMITA, Yoshihiro ,  LIFF, Shawna

Inventor： HU, Chuan ,  ELSHERBINI, Adel A. ,  TOMITA, Yoshihiro ,  LIFF, Shawna

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/60

CPC classification number: H05K1/0283 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/1515 ,  H01L2924/181 ,  H05K1/036 ,  H05K1/185 ,  H05K3/1275 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09263 ,  H05K2201/10151 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure describe a wavy interconnect for bendable and stretchable devices and associated techniques and configurations. In one embodiment, an interconnect assembly includes a flexible substrate defining a plane and a wavy interconnect disposed on the flexible substrate and configured to route electrical signals of an integrated circuit (IC) device in a first direction that is coplanar with the plane, the wavy interconnect having a wavy profile from a second direction that is perpendicular to the first direction and coplanar with the plane. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于可弯曲和可拉伸装置的波浪互连以及相关技术和配置。 在一个实施例中，互连组件包括限定平面的柔性衬底和布置在柔性衬底上的波纹互连，并且被配置成沿与平面共面的第一方向布置集成电路（IC）器件的电信号，波形 互连件具有从垂直于第一方向并与该平面共面的第二方向的波状轮廓。 可以描述和/或要求保护其他实施例。

公开(公告)号：WO2013095444A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066546

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  HU, Chuan

Inventor： HU, Chuan

IPC: H01L23/64 ,  H01L25/16

CPC classification number: H01L23/3736 ,  H01L21/4871 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/00 ,  H01L2224/82

Abstract: Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.

Abstract translation: 描述了封装的半导体管芯和CTE工程管芯对以及形成封装的半导体管芯和CTE工程管芯对的方法。 例如，半导体封装包括衬底。 半导体管芯被嵌入基板中并具有表面积。 将CTE工程管芯嵌入衬底并耦合到半导体管芯。 CTE工程模具的表面积相同并与半导体管芯的表面积对准。

公开(公告)号：WO2012129153A3

公开(公告)日：2012-12-27

申请号：PCT/US2012029617

申请日：2012-03-19

Applicant: INTEL CORP ,  HU CHUAN ,  LIFF SHAWNA M ,  CLEMONS GREGORY S

Inventor： HU CHUAN ,  LIFF SHAWNA M ,  CLEMONS GREGORY S

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/10156 ,  H01L2224/1131 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13111 ,  H01L2224/16111 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1624 ,  H01L2224/2929 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2224/81805

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Abstract translation: 本公开涉及制造微电子封装的领域，其中空腔被形成在沉积在第一衬底上的电介质层中以维持焊接互连之间的分隔。 在一个实施例中，空腔可以具有倾斜的侧壁。 在另一个实施例中，焊膏可以沉积在空腔中并且在加热时可以形成焊料结构。 在其他实施例中，焊料结构可以放置在空腔中或者可以形成在第一衬底可以连接到的第二衬底上。 在其他实施例中，可以在第一基板和第二基板两者上形成焊料结构。 焊料结构可以用于通过与第二衬底上的接触区或焊料结构接触和回流来形成焊料互连。

公开(公告)号：WO2006039176A1

公开(公告)日：2006-04-13

申请号：PCT/US2005/033928

申请日：2005-09-21

Applicant: INTEL CORPORATION ,  HU, Chuan ,  TOWLE, Steven

Inventor： HU, Chuan ,  TOWLE, Steven

IPC: H01L23/373

CPC classification number: H01L23/49568 ,  H01L23/142 ,  H01L23/367 ,  H01L23/373 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A thinned die is disposed on a heat sink and bonded by a thermal interface material (TIM) that includes a gold-tin solder. The thinned die exhibits a die-effective coefficient of thermal expansion (CTE) that substantially matches the CTE of the heat sink. A process of bonding the die includes thermal bonding. A process of bonding the thinned die to a heat sink before bonding the die to an electrical interposer. A computing system includes a semconductive die that is gold-tin bonded to the heat sink, and it is coupled to at least one input-output device.

Abstract translation: 减薄的模具设置在散热器上并且通过包含金锡焊料的热界面材料（TIM）结合。 薄型模具表现出与散热器的CTE基本相匹配的有效的热膨胀系数（CTE）。 模具的结合工艺包括热粘合。 在将模具粘合到电插入器之前，将薄模具粘合到散热器上的过程。 一种计算系统包括一金属锡结合到该散热器上的导电管芯，并且该导电管芯耦合至少一个输入输出装置。

公开(公告)号：WO2011084216A2

公开(公告)日：2011-07-14

申请号：PCT/US2010/054931

申请日：2010-11-01

Applicant: INTEL CORPORATION ,  MA, Qing ,  HU, Chuan ,  MORROW, Patrick

Inventor： MA, Qing ,  HU, Chuan ,  MORROW, Patrick

IPC: H01L23/485 ,  H05K3/46

CPC classification number: H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）装置的基板的实施例。 衬底包括由已经结合在一起的两个或更多个离散的玻璃层组成的芯。 可以在相邻的玻璃层之间设置单独的粘合层，以将这些层连接在一起。 衬底还可以包括在多层玻璃芯的相对侧上或者可能在芯的一侧上的堆积结构。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸通过多层玻璃芯，并且一个或多个导体可以与布置在芯上的积聚结构电耦合。 描述和要求保护其他实施例。

公开(公告)号：WO2016018237A1

公开(公告)日：2016-02-04

申请号：PCT/US2014/048510

申请日：2014-07-28

Applicant: INTEL CORPORATION ,  HU, Chuan ,  CHIU, Chia-Pin ,  SWAN, Johanna

Inventor： HU, Chuan ,  CHIU, Chia-Pin ,  SWAN, Johanna

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/82039 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/3511

Abstract: An apparatus is described having a build-up layer. The build-up layer has a pad side of multiple die pressed into a bottom side of the build-up layer. The multiple die have wide pads to facilitate on wafer testing of the multiple die. The wide pads are spaced a minimum distance permitted by a manufacturing process used to manufacture their respective die. The build-up layer above the wide pads is removed. The apparatus also includes metallization on a top side of the build-up layer that substantially fills regions above the wide pads. The metallization includes lands above the wide pads and multiple wires between the wide pads.

Abstract translation: 描述了具有堆积层的装置。 堆积层具有压入堆积层的底侧的多个模头的垫侧。 多个管芯具有宽焊盘，以便于对多个管芯进行晶片测试。 宽焊盘间隔开用于制造其相应管芯的制造工艺允许的最小距离。 移除宽垫上方的堆积层。 该装置还包括在积层的顶侧上的金属化，其基本上填充宽焊盘上方的区域。 金属化包括宽焊盘上方的焊盘和宽焊盘之间的多条焊丝。

公开(公告)号：WO2013184145A1

公开(公告)日：2013-12-12

申请号：PCT/US2012/041714

申请日：2012-06-08

Applicant: INTEL CORPORATION ,  HU, Chuan

Inventor： HU, Chuan

IPC: H01L23/48 ,  H01L23/28

CPC classification number: H01L23/298 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00

Abstract: A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material, wherein the encapsulated structure may have an active surface proximate the active surfaces of the plurality of microelectronic devices, and wherein at least one of the plurality of microelectronic devices may have a height greater than another of the plurality of microelectronic devices (e.g. non-coplanar). The microelectronic package further includes a bumpless build-up layer structure formed proximate the encapsulated structure active surface. The microelectronic package may also have an active surface microelectronic device positioned proximate the encapsulated structure active surface and in electrical contact with at least one of the plurality of microelectronic devices of the encapsulated substrate.

Abstract translation: 一种微电子封装，其具有封装的衬底，其包括封装在封装材料内的多个微电子器件，其中所述封装结构可具有靠近所述多个微电子器件的有源表面的有源表面，并且其中所述多个微电子器件中的至少一个 可以具有大于多个微电子器件中的另一个的高度（例如非共面）。 微电子封装还包括在封装结构有源表面附近形成的无凸起的积层层结构。 微电子封装还可以具有位于封装结构有源表面附近并与封装衬底的多个微电子器件中的至少一个电接触的有源表面微电子器件。

公开(公告)号：WO2013095442A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066542

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  HU, Chuan

Inventor： HU, Chuan

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L23/49811 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/11332 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/82 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81

Abstract: Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages are described. For example, a method of fabricating a semiconductor structure includes forming an insulative material stack above a plurality of solder bump landing pads. The solder bump landing pads are above an active side of a semiconductor die. A plurality of trenches is formed in the insulative material stack by laser ablation to expose a corresponding portion of each of the plurality of solder bump landing pads. A solder bump is formed in each of the plurality of trenches. A portion of the insulative material stack is then removed.

Abstract translation: 描述了具有激光烧蚀和所得半导体结构和封装的与焊帽（DISC）形成的密集互连。 例如，制造半导体结构的方法包括在多个焊料凸点焊盘上方形成绝缘材料堆叠。 焊料凸块接合焊盘在半导体管芯的有效侧之上。 通过激光烧蚀在绝缘材料堆叠中形成多个沟槽，以暴露多个焊料凸块着陆焊盘中的每一个的对应部分。 在多个沟槽的每一个中形成焊料凸块。 然后去除绝缘材料堆叠的一部分。

公开(公告)号：WO2011084216A3

公开(公告)日：2011-09-09

申请号：PCT/US2010054931

申请日：2010-11-01

Applicant: INTEL CORP ,  MA QING ,  HU CHUAN ,  MORROW PATRICK

Inventor： MA QING ,  HU CHUAN ,  MORROW PATRICK

IPC: H01L23/485 ,  H05K3/46

CPC classification number: H01L23/49822 ,  B32B2457/08 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05442 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15788 ,  H01L2924/16251 ,  H05K3/42 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/096 ,  Y10T156/10 ,  H01L2924/00

Abstract: Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Abstract translation: 公开了用于集成电路（IC）器件的衬底的实施例。 衬底包括由两个或更多个已经粘合在一起的分立的玻璃层组成的芯。 单独的结合层可以设置在相邻的玻璃层之间以将这些层结合在一起。 衬底还可以包括在多层玻璃芯的相对侧上的堆积结构，或者可能在芯的一侧上。 导电端子可以形成在基板的两侧，并且IC管芯可以与基板的一侧上的端子耦合。 相对侧上的端子可以与诸如电路板的下一级组件耦合。 一个或多个导体延伸穿过多层玻璃芯，并且一个或多个导体可以与设置在芯上的积层结构电耦合。 描述并要求保护其他实施例。