公开(公告)号：WO2019199472A1

公开(公告)日：2019-10-17

申请号：PCT/US2019/024647

申请日：2019-03-28

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  KILIC, Bahattin ,  ZHAO, Jie-Hua ,  HU, Kunzhong ,  RYU, Suk-Kyu

IPC: H01L23/00 ,  H01L25/065 ,  G06F13/40 ,  G06F15/78

Abstract: Multi-chip systems (100) and structures for modular scaling are described. In some embodiments an interfacing bar (150) is utilized to couple adjacent chips (102, 104). For example, a communication bar (150) may utilized to coupled logic chips (104), and memory bar (150) may be utilized to couple multiple memory chips (102) to a logic chip (104).

公开(公告)号：WO2016081182A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/058474

申请日：2015-10-30

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  CARSON, Flynn P.

IPC: H01L25/03 ,  H01L21/98 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/525 ,  H01L23/552 ,  H01L24/19 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2224/81

Abstract: Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the second routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.

Abstract translation: 描述了扇出晶片级封装（FOWLP）和形成方法。 在一个实施例中，包装包括第一布线层，第一布线层的顶侧上的第一管芯，以及将第一管芯封装在第一布线层上的第一模制化合物。 第一多个导电柱从第一路由层的底侧延伸。 第二管芯位于第二布线层的顶侧，并且第一多个导电柱位于第二布线层的顶侧。 第二模塑料在第二路由层上封装第一模塑料，第一路由层，第一多个导电柱和第二模。 在一个实施例中，多个导电凸块（例如焊球）从第二布线层的底侧延伸。

公开(公告)号：WO2023049597A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/075471

申请日：2022-08-25

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  YEH, Jung-Cheng ,  HU, Kunzhong ,  CAMENFORTE, Raymundo ,  HOFFMANN, Thomas

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L23/66

Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

公开(公告)号：WO2021201990A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/017445

申请日：2021-02-10

Applicant: APPLE INC.

Inventor： CHEN, Wei ,  ZHAO, Jie-Hua ,  ZHAI, Jun ,  CHANG, Po-Hao ,  LIN, Hsien-Che ,  KE, Ying-Chieh ,  HU, Kunzhong

IPC: H01L23/04 ,  H01L23/16 ,  H01L23/367 ,  H01L25/065 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L23/24 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L2924/15311 ,  H01L2924/1615 ,  H01L2924/16151 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/164 ,  H01L2924/19105 ,  H01L2924/3511

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

公开(公告)号：WO2020112505A3

公开(公告)日：2020-06-04

申请号：PCT/US2019/062702

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  LAI, Kwan-Yu ,  HU, Kunzhong ,  RAMACHANDRAN, Vidhya

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/60 ,  H01L23/29

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure (310) to connect a die set (110, 110) embedded in an inorganic gap fill material (130).

公开(公告)号：WO2020112505A2

公开(公告)日：2020-06-04

申请号：PCT/US2019/062702

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  ZHAI, Jun ,  LAI, Kwan-Yu ,  HU, Kunzhong ,  RAMACHANDRAN, Vidhya

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L21/66 ,  H01L23/60

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：WO2018226394A2

公开(公告)日：2018-12-13

申请号：PCT/US2018/033813

申请日：2018-05-22

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  ZHONG, Chonghua ,  HU, Kunzhong

Abstract: Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

公开(公告)号：WO2016164119A1

公开(公告)日：2016-10-13

申请号：PCT/US2016/020289

申请日：2016-03-01

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  ZHONG, Chonghua ,  PANG, Mengzhi ,  YANG, Se Young

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/83

Abstract: Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) (130) formed directly on a top die (110), and a bottom die (150) mounted on a back surface of the RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装包括直接形成在顶模（110）上的再分配层（RDL）（130）和安装在RDL的后表面上的底模（150）。

公开(公告)号：WO2016140819A2

公开(公告)日：2016-09-09

申请号：PCT/US2016/018804

申请日：2016-02-19

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  LAI, Kwan-Yu ,  PANG, Mengzhi ,  ZHONG, Chonghua ,  YANG, Se Young

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08167 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/81193 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2224/27 ,  H01L2924/014

Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

Abstract translation: 描述了包装和形成方法。 在一个实施例中，封装系统（SiP）包括第一和第二再分配层（RDL）以及附接到第一RDL的前侧和后侧的多个管芯。 第一和第二RDL与从第一RDL的后侧延伸到第二RDL的前侧的多个导电柱连接在一起。