公开(公告)号：WO2010086153A1

公开(公告)日：2010-08-05

申请号：PCT/EP2010/000491

申请日：2010-01-27

Applicant: ADVANCED MICRO DEVICES, INC ,  MULFINGER, Robert ,  WEI, Andy ,  HOENTSCHEL, Jan ,  PAPAGEORGIOU, Vassilios ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： MULFINGER, Robert ,  WEI, Andy ,  HOENTSCHEL, Jan ,  PAPAGEORGIOU, Vassilios

IPC: H01L21/266 ,  H01L21/336 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/266 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/823418 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/66659

Abstract: In sophisticated semiconductor devices and asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.

Abstract translation: 在复杂的半导体器件和不对称晶体管配置中，可以在不对称阱注入的基础上获得，同时避免倾斜的注入工艺。 为此，可以形成渐变注入掩模，例如渐变抗蚀剂掩模，其与不对称晶体管的源极侧相比在漏极侧可具有更高的离子阻挡能力。 例如，可以在具有高度性能增益的非倾斜注入工艺的基础上获得非对称构造，并且可以不考虑所考虑的技术标准而实现。

公开(公告)号：WO2007064982A1

公开(公告)日：2007-06-07

申请号：PCT/US2006/046174

申请日：2006-11-29

Applicant: INTEL CORPORATION ,  HATTENDORF, Michael, L. ,  BRASK, Justin, K. ,  SANDFORD, Justin, S. ,  KAVALIEROS, Jack, T. ,  METZ, Matthew, V.

Inventor： HATTENDORF, Michael, L. ,  BRASK, Justin, K. ,  SANDFORD, Justin, S. ,  KAVALIEROS, Jack, T. ,  METZ, Matthew, V.

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/265 ,  H01L21/311 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L21/3115

CPC classification number: H01L21/28114 ,  H01L21/26586 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32136 ,  H01L21/32137 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Embodiments of the invention provide a device with a reverse-tapered gate electrode and a gate dielectric layer with a length close to that of the gate length. In an embodiment, this may be done by altering portions of a blanket dielectric layer with one or more angled ion implants, then removing the altered portions of the blanket dielectric layer.

Abstract translation: 本发明的实施例提供一种具有反向锥形栅极电极和栅极电介质层的器件，其长度接近栅极长度。 在一个实施例中，这可以通过用一个或多个成角度的离子注入改变覆盖介电层的部分，然后去除覆盖介电层的改变的部分来完成。

公开(公告)号：WO2006009782A3

公开(公告)日：2007-05-31

申请号：PCT/US2005021317

申请日：2005-06-17

Applicant: ON INTERNATIONAL INC ,  BURGENER II ROBERT H ,  FELIX ROGER L ,  RENLUND GARY M

Inventor： BURGENER II ROBERT H ,  FELIX ROGER L ,  RENLUND GARY M

IPC: H01L29/12 ,  C01G9/02 ,  H01L21/00 ,  H01L21/20 ,  H01L21/28 ,  H01L21/31 ,  H01L21/3115 ,  H01L21/316 ,  H01L21/363 ,  H01L21/365 ,  H01L21/469 ,  H01L23/58 ,  H01L27/15 ,  H01L29/225 ,  H01L29/26 ,  H01L31/0296 ,  H01L31/0328 ,  H01L31/12 ,  H01L33/28 ,  H01S5/30 ,  H01S5/327 ,  H01S5/347

CPC classification number: H01L33/28 ,  B82Y20/00 ,  C01G9/02 ,  C01P2006/40 ,  C30B25/02 ,  C30B29/16 ,  C30B29/48 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/02579 ,  H01L21/3115 ,  H01L21/316 ,  H01L23/5329 ,  H01L29/225 ,  H01L31/02963 ,  H01L33/025 ,  H01L33/285 ,  H01L2924/0002 ,  H01S5/305 ,  H01S5/3054 ,  H01S5/327 ,  H01S5/347 ,  H01L2924/00

Abstract: A persistent p-type group II-VI semiconductor material is disclosed containing atoms of group II elements, atoms of group VI elements, and a p-type dopant which replaces atoms of the group VI element in the semiconductor material. The p-type dopant has a negative oxidation state. The p-type dopant causes formation of vacancies of atoms of the group II element in the semiconductor material. Fabrication methods and solid state devices containing the group II-VI semiconductor material are disclosed.

Abstract translation: 公开了一种持续性的p型II-VI族半导体材料，其包含II族元素的原子，VI族元素的原子和替代半导体材料中的VI族元素的原子的p型掺杂剂。 p型掺杂剂具有负氧化态。 p型掺杂剂引起半导体材料中II族元素的原子空位的形成。 公开了含有II-VI族半导体材料的制造方法和固态器件。

公开(公告)号：WO2004061910A3

公开(公告)日：2004-09-02

申请号：PCT/US0336372

申请日：2003-11-12

Applicant: INTEL CORP

Inventor： HARELAND SCOTT ,  LINDERT NICK ,  ARGHAVANI REZA ,  CHAU ROBERT

IPC: H01L21/265 ,  H01L21/266 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/31111 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/31053 ,  H01L21/3115

Abstract: A method for anisotropically and selectively removing a dielectric thin film layer (102, 103) from a substrate layer (100) is disclosed, wherein the dielectric layer is subjected to ion implantation (122) prior to wet etching. This method may be applied adjacent to a structure such as a gate electrode within a microelectronic structure to prevent undercutting of the dielectric material to be preserved between the gate electrode and the substrate layer, as may happen with more isotropic etching techniques.

Abstract translation: 公开了一种用于从基底层（100）各向异性地选择性地去除电介质薄膜层（102,103）的方法，其中介电层在湿蚀刻之前进行离子注入（122）。 该方法可以与微电子结构内的诸如栅电极的结构相邻地施加，以防止在栅电极和衬底层之间保留的电介质材料的底切，这可能由于更多的各向同性蚀刻技术而发生。

公开(公告)号：WO99065070A2

公开(公告)日：1999-12-16

申请号：PCT/IB1999/001003

申请日：1999-06-03

IPC: H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3115 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L21/31155

Abstract: The invention relates to a method of manufacturing a (horizontal) MOST, as used, for example, in (BI)CMOS ICs. On either side of a gate electrode (2), the surface of a silicon substrate (10, 11) which is positioned above a gate oxide (1A) is provided with a dielectric layer (1B) at the location where a source (3) and drain (4) are to be formed, which dielectric layer includes a thermal oxide layer (1B) to be formed as the starting layer. The source (3) and/or drain (4) is/are provided with LDD regions (3A, 4A) and the remaining parts (3B, 4B) of the source (3) and drain (4) are provided by an ion implantation (I1) of doping atoms into the silicon substrate (10, 11). A MOST obtained in this way still suffers from so-called short-channel effects, resulting in a substantial dependence of the threshold voltage upon the length of the gate electrode (2), in particular in the case of very short lengths of the gate electrode (2). In a method according to the invention, the LDD regions (3A, 4A) are made as follows: in a first step, suitable doping atoms (D) are implanted into the dielectric layer (1B), in a second ion implantation (I2), and subsequently in a second step, a part of the doping atoms (D) is diffused from the dielectric layer (1B) into the silicon substrate (10, 11), whereby the LDD regions (3A, 4A) are formed. This method enables a MOST with excellent properties to be obtained, for example with a flatter profile of the threshold voltage versus the gate-electrode (2) length (curve 130) than in conventionally made MOSTs (curve 131). This result is obtained in a simple and reproducible manner.

Abstract translation: 本发明涉及制造（水平）MOST的方法，例如在（BI）CMOS IC中使用的MOST。 在栅电极（2）的任一侧，位于栅极氧化物（1A）上方的硅衬底（10,11）的表面在源极（3）的位置处设置有电介质层（1B） 并形成漏极（4），该介质层包括形成为起始层的热氧化物层（1B）。 源极（3）和/或漏极（4）设置有LDD区域（3A，4A），源极（3）和漏极（4）的其余部分（3B，4B）由离子注入 （I1）掺杂到硅衬底（10,11）中。 以这种方式获得的MOST仍然遭受所谓的短沟道效应，导致阈值电压对栅电极（2）的长度的实质依赖性，特别是在非常短的栅电极长度的情况下 （2）。 在根据本发明的方法中，LDD区域（3A，4A）如下制造：在第一步骤中，在第二离子注入（I2）中，将合适的掺杂原子（D）注入到介电层（1B） ，随后在第二步骤中，掺杂原子（D）的一部分从电介质层（1B）扩散到硅衬底（10,11）中，由此形成LDD区域（3A，4A）。 该方法使得能够获得具有优异性能的MOST，例如与常规制作的MOST（曲线131）相比，阈值电压相对于栅电极（2）长度（曲线130）的平坦轮廓。 该结果以简单且可再现的方式获得。

公开(公告)号：WO99010924A1

公开(公告)日：1999-03-04

申请号：PCT/US1998/017585

申请日：1998-08-25

IPC: H01L21/28 ,  H01L21/3115 ,  H01L21/318 ,  H01L21/322 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L21/76832 ,  H01L21/31155 ,  H01L21/3221 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/66825

Abstract: A semiconductor device (400) formed in a semiconductor substrate (402) with a low hydrogen content barrier layer (432) formed over the semiconductor device (400). The barrier layer (432) is implanted with phosphorous ions (429). The semiconductor device (400) may have a hydrogen getter layer (424) formed under the barrier layer (432). The barrier layer (432) is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer (424) is P-doped film having a thickness between 1000 and 2000 Angstroms and is a PSG, BPSG, PTEOS deposited oxide film, or BPTEOS deposited oxide film. Interconnects (438) are made by a tungsten damascene process.

Abstract translation: 形成在形成在半导体器件（400）上的低氢含量阻挡层（432）的半导体衬底（402）中的半导体器件（400）。 阻挡层（432）注入磷离子（429）。 半导体器件（400）可以具有形成在阻挡层（432）下方的吸氢剂层（424）。 阻挡层（432）是高温PECVD氮化物膜，高温PECVD氮氧化物膜或高温LPCVD氮化物膜。 吸氢剂层（424）是厚度在1000和2000埃之间的P掺杂膜，是PSG，BPSG，PTEOS沉积氧化物膜或BPTEOS沉积氧化物膜。 互连（438）由钨镶嵌工艺制成。

公开(公告)号：WO2022232224A1

公开(公告)日：2022-11-03

申请号：PCT/US2022/026465

申请日：2022-04-27

Applicant: APPLIED MATERIALS, INC.

Inventor： SUBRAHMANYAN, Pradeep K. ,  KANG, Sean S. ,  VARGHESE, Sony

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/66 ,  H01L21/3115 ,  H01L21/67

Abstract: Provided are methods of reducing the stress of a semiconductor wafer. A wafer map of a free-standing wafer is created using metrology tools. The wafer map is then converted into a power spectral density (PSD) using a spatial frequency scale. The fundamental component of bow is then compensated with a uniform film, e.g., silicon nitride (SiN), deposited on the back side of the wafer.

公开(公告)号：WO2021262841A8

公开(公告)日：2021-12-30

申请号：PCT/US2021/038668

申请日：2021-06-23

Applicant: L'AIR LIQUIDE, SOCIETE ANONYME POUR L'ETUDE ET L'EXPLOITATION DES PROCEDES GEORGES CLAUDE ,  AMERICAN AIR LIQUIDE, INC.

Inventor： MARCHEGIANI, Fabrizio

IPC: H01L21/3065 ,  H01L27/11582 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32137 ,  H01L21/76802 ,  H01L27/1157 ,  H01L27/11578

Abstract: Disclosed are methods for etching a silicon-containing film to form a patterned structure, methods for reinforcing and/or strengthening and/or minimizing damage of a patterned mask layer while forming a patterned structure and methods for increasing etch resistance of a patterned mask layer in a process of forming a patterned structure. The methods include using an activated iodine-containing etching compound having the formula CnHxFylz, wherein 4≤ n ≤ 10, 0 ≤ x ≤ 21, 0 ≤ y ≤ 21, and 1 ≤ z ≤ 4 as an etching gas. The activated iodine-containing etching compound produces iodine ions, which are implanted into the patterned hardmask layer, thereby strengthening the patterned mask layer.

公开(公告)号：WO2021257277A1

公开(公告)日：2021-12-23

申请号：PCT/US2021/035417

申请日：2021-06-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： ABDELRAHAMAN, Ramey, M. ,  WU, Jeslin, J. ,  TIWARI, Chandra ,  SHROTRI, Kunal ,  LENGADE, Swapnil

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/66 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/31111 ,  H01L21/3115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The insulative levels have a same primary composition as one another. At least one of the insulative levels is compositionally different relative to others of the insulative levels due to said at least one of the insulative levels including dopant dispersed within the primary composition. An opening extends vertically through the stack. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：WO2019077156A1

公开(公告)日：2019-04-25

申请号：PCT/EP2018/078832

申请日：2018-10-22

Applicant: THALES

Inventor： LEGAGNEUX, Pierre ,  PRIBAT, Didier ,  COJOCARU, Costel-Sorin ,  SERVET, Bernard

IPC: C23C14/48 ,  C23C14/58 ,  C23C14/06 ,  C23C14/00 ,  C23C14/02 ,  H01L29/66 ,  H01L29/24 ,  H01L21/02 ,  H01L21/3115 ,  H01J37/317

Abstract: L'invention concerne un procédé de réalisation d'au moins une monocouche (L) d'un matériau bidimensionnel (mat2D), ledit matériau bidimensionnel comprenant au moins un élément M métal et un élément X chalcogène, le procédé comprenant : -une étape (100) d'apport de l'élément M et une étape (200) d'apport de l'élément X de manière à former, dans un substrat (Sub, L Au ) une zone (Z[M+X]) comprenant des atomes de l'élément M et des atomes de l'élément X, -une étape de recuit (300) de manière à former l'au moins une monocouche (L) de matériau bidimensionnel (mat2D) par diffusion desdits atomes dans ledit substrat, et dans lequel chaque étape d'apport (100,200) est réalisée par implantation ionique.