公开(公告)号：WO2010097191A1

公开(公告)日：2010-09-02

申请号：PCT/EP2010/001092

申请日：2010-02-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  FEUSTEL, Frank ,  FROHBERG, Kai ,  WERNER, Thomas ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： FEUSTEL, Frank ,  FROHBERG, Kai ,  WERNER, Thomas

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: In a metallization system of a complex semiconductor device, metal pillars (271) such as copper pillars may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.

Abstract translation: 在复杂半导体器件的金属化系统中，诸如铜柱的金属柱（271）可以形成为钉状构造，以便减少作用在金属化系统上的最大机械应力，同时提供所需的接触表面用于连接到 封装衬底。 可以基于适当配置的抗蚀剂掩模获得钉状构造。

公开(公告)号：WO2010086154A1

公开(公告)日：2010-08-05

申请号：PCT/EP2010/000492

申请日：2010-01-27

Applicant: 5ADVANCED MICRO DEVICES, INC ,  HOENTSCHEL, Jan ,  PAPAGEORGIOU, Vassilios ,  GRIEBENOW, Uwe ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： HOENTSCHEL, Jan ,  PAPAGEORGIOU, Vassilios ,  GRIEBENOW, Uwe

IPC: H01L21/336 ,  H01L21/225 ,  H01L21/265 ,  H01L29/51 ,  H01L29/165 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/2254 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78621

Abstract: The dopant profile of a transistor may be obtained on the basis of an in situ doped strain inducing semiconductor alloy wherein a graded dopant concentration may be established along the height direction. Consequently, the semiconductor alloy may be positioned in close proximity to the channel region, thereby enhancing the overall strain inducing efficiency, while not unduly compromising the finally obtained dopant profile. Furthermore, additional implant species may be incorporated prior to selectively growing the semiconductor alloy thereby avoiding implantation induced relaxation of the internal strain.

Abstract translation: 可以基于原位掺杂的应变诱导半导体合金获得晶体管的掺杂物分布，其中可以沿着高度方向建立渐变掺杂剂浓度。 因此，可以将半导体合金定位在靠近沟道区的位置，从而提高整个应变诱导效率，同时不会过度损害最终获得的掺杂剂分布。 此外，在选择性地生长半导体合金之前可以并入额外的植入物种，从而避免植入引起的内部应变松弛。

公开(公告)号：WO2010097190A1

公开(公告)日：2010-09-02

申请号：PCT/EP2010/001091

申请日：2010-02-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  AUBEL, Oliver ,  HOHAGE, Joerg ,  FEUSTEL, Frank ,  PREUSSE, Axel ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： AUBEL, Oliver ,  HOHAGE, Joerg ,  FEUSTEL, Frank ,  PREUSSE, Axel

IPC: H01L21/768

CPC classification number: H01L21/76826 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76864 ,  Y10S438/906

Abstract: During the formation of complex metallization systems a conductive cap layer (122C) may be formed on a copper-containing metal region (122A) in order to enhance the electromigration behaviour without negatively affecting the overall conductivity. At the same time, a thermo chemical treatment may be performed so as to provide for superior surface conditions of the sensitive dielectric material (121) and also to suppress carbon depletion, which may conventionally result in a significant variability of material characteristics of sensitive ULK materials.

Abstract translation: 在形成复杂的金属化系统期间，可以在含铜金属区域（122A）上形成导电覆盖层（122C），以增强电迁移行为，而不会不利地影响整个导电性。 同时，可以进行热化学处理，以便提供敏感电介质材料（121）的优异表面条件并且还抑制碳消耗，这常常导致敏感的ULK材料的材料特性的显着变化 。

公开(公告)号：WO2010086153A1

公开(公告)日：2010-08-05

申请号：PCT/EP2010/000491

申请日：2010-01-27

Applicant: ADVANCED MICRO DEVICES, INC ,  MULFINGER, Robert ,  WEI, Andy ,  HOENTSCHEL, Jan ,  PAPAGEORGIOU, Vassilios ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： MULFINGER, Robert ,  WEI, Andy ,  HOENTSCHEL, Jan ,  PAPAGEORGIOU, Vassilios

IPC: H01L21/266 ,  H01L21/336 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/266 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/823418 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/66659

Abstract: In sophisticated semiconductor devices and asymmetric transistor configuration may be obtained on the basis of an asymmetric well implantation while avoiding a tilted implantation process. For this purpose a graded implantation mask may be formed, such as a graded resist mask, which may have a higher ion blocking capability at the drain side compared to the source side of the asymmetric transistor. For instance, the asymmetric configuration may be obtained on the basis of a non-tilted implantation process with a high degree of performance gain and may be accomplished irrespective of the technology standard under consideration.

Abstract translation: 在复杂的半导体器件和不对称晶体管配置中，可以在不对称阱注入的基础上获得，同时避免倾斜的注入工艺。 为此，可以形成渐变注入掩模，例如渐变抗蚀剂掩模，其与不对称晶体管的源极侧相比在漏极侧可具有更高的离子阻挡能力。 例如，可以在具有高度性能增益的非倾斜注入工艺的基础上获得非对称构造，并且可以不考虑所考虑的技术标准而实现。

公开(公告)号：WO2010076017A1

公开(公告)日：2010-07-08

申请号：PCT/EP2009/009306

申请日：2009-12-29

Applicant: ADVANCED MICRO DEVICES, INC ,  KRONHOLZ, Stephan ,  PAPAGEORGIOU, Vassilios ,  BEERNINK, Gunda ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： KRONHOLZ, Stephan ,  PAPAGEORGIOU, Vassilios ,  BEERNINK, Gunda

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7848

Abstract: In a transistor a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain- inducing semiconductor alloy. For this purpose, two or more "disposable" spacer elements of different etch behaviour may be used in order to define different lateral off-sets at different depths of the corresponding cavities. Consequently, enhanced uniformity and thus reduced transistor variability may be accomplished even for sophisticated semiconductor devices.

Abstract translation: 在晶体管中，诸如硅/锗，硅/碳等的应变诱导半导体合金可以通过提供逐渐形成的空腔而非常靠近沟道区域，然后可以用应变诱导半导体合金填充。 为此，可以使用不同蚀刻行为的两个或更多个“一次性”间隔元件，以便在相应空腔的不同深度处限定不同的侧向偏移。 因此，即使对于复杂的半导体器件也可以实现增强的均匀性并因此降低晶体管的变化性。

公开(公告)号：WO2010076019A1

公开(公告)日：2010-07-08

申请号：PCT/EP2009/009308

申请日：2009-12-29

Applicant: ADVANCED MICRO DEVICES, INC ,  FEUSTEL, Frank ,  WERNER, Thomas ,  FROHBERG, Kai ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： FEUSTEL, Frank ,  WERNER, Thomas ,  FROHBERG, Kai

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76804 ,  H01L21/76813

Abstract: In a metallization system of a semiconductor device a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may once, or several times be eroded in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto.

Abstract translation: 在半导体器件的金属化系统中，可以通过修改相应的蚀刻序列来提供过渡通孔的增加的渐缩度。 例如，为了增加对应的掩模开口的横向尺寸，用于形成通路孔的抗蚀剂掩模可以被一次或几次侵蚀。 由于显着的渐缩度，在随后的电化学沉积过程中可以实现增强的沉积条件，用于通常填充通孔开口和与其连接的宽沟槽。

公开(公告)号：WO2010076018A1

公开(公告)日：2010-07-08

申请号：PCT/EP2009/009307

申请日：2009-12-29

Applicant: ADVANCED MICRO DEVICES, INC ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG ,  KRONHOLZ, Stephan ,  OTT, Andreas

Inventor： KRONHOLZ, Stephan ,  OTT, Andreas

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/84

Abstract: A threshold adjusting semiconductor material, such as a silicon/germanium alloy may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced.

Abstract translation: 基于增强的沉积均匀性，可以选择性地为一种类型的晶体管提供阈值调节半导体材料，例如硅/锗合金。 为此，可以将半导体合金沉积在任何晶体管的有源区上，并且随后可以基于高度可控的图案化状态来图案化。 因此，阈值变化可能降低。

公开(公告)号：WO2010086152A1

公开(公告)日：2010-08-05

申请号：PCT/EP2010/000490

申请日：2010-01-27

Applicant: ADVANCED MICRO DEVICES, INC. ,  KRONHOLZ, Stephan ,  NAUMANN, Andreas ,  BEERNINK, Gunda ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG

Inventor： KRONHOLZ, Stephan ,  NAUMANN, Andreas ,  BEERNINK, Gunda

IPC: H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823412 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878

Abstract: The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma assisted etch process, thereby simultaneously providing for a superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability.

Abstract translation: 用于沉积阈值调节半导体合金（例如硅/锗合金）的选择性外延生长工艺中的生长速率可以通过在执行选择性外延生长工艺之前执行等离子体辅助蚀刻工艺来增强。 例如，可以基于等离子体辅助蚀刻工艺对掩模层进行图案化，从而在随后的生长过程期间同时提供优异的器件形貌。 因此，可以以增强的厚度均匀性沉积阈值调节材料，从而降低总体阈值变化。

公开(公告)号：WO2010060639A1

公开(公告)日：2010-06-03

申请号：PCT/EP2009/008472

申请日：2009-11-27

Applicant: ADVANCED MICRO DEVICES INC ,  AMD FAB 36 LIMITED LIABILITY COMPANY & CO. KG ,  WERNER, Thomas ,  FROHBERG, Kai ,  FEUSTEL, Frank

Inventor： WERNER, Thomas ,  FROHBERG, Kai ,  FEUSTEL, Frank

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Air gaps may be formed in a metallization layer of a microstructure device on the basis of a patterning sequence in which also respective via openings are formed. Thereafter, the via openings and the air gaps may be closed by a deposition process without significantly affecting the interior of the corresponding openings. Thereafter, the further processing may be continued by forming respective trenches while maintaining integrity of the covered air gaps. Thus, the relative permittivity of the interlayer dielectric material may efficiently be reduced without adding additional process complexity.

Abstract translation: 基于形成相应的通路孔的图案化顺序，可以在微结构器件的金属化层中形成气隙。 此后，通孔和气隙可以通过沉积工艺封闭，而不会明显地影响相应的开口的内部。 此后，可以通过在保持覆盖的气隙的完整性的同时形成相应的沟槽来继续进一步的处理。 因此，层间绝缘材料的相对介电常数可以有效地降低，而不增加额外的工艺复杂性。