公开(公告)号：WO2006096813A3

公开(公告)日：2006-09-14

申请号：PCT/US2006/008449

申请日：2006-03-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SONY CORPORATION ,  NGUYEN, Son, V. ,  LANE, Sarah, L. ,  LINIGER, Eric, G. ,  IDA, Kensaku ,  RESTAINO, Darryl, D.

Inventor： NGUYEN, Son, V. ,  LANE, Sarah, L. ,  LINIGER, Eric, G. ,  IDA, Kensaku ,  RESTAINO, Darryl, D.

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

Abstract: A material stack (12) is provided comprising one or more films (14) that have a crack velocity of about IE- 10 m/sec or greater and at least one monolayer (16) within or in direct contact with the one or more films (14), wherein the at least one monolayer (16) reduces the crack velocity of the material stack (12) to a value of less than lE-10 m/sec. The one or more films ( 14) are not limited to low k dielectrics, but may include materials such as a metal. In a preferred embodiment, a low k dielectric stack (12) is provided, having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack (12) are improved by introducing at least one nanolayer (16) into the dielectric stack (12). The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of me films within the stack (12) and without the need of subjecting the inventive dielectric stack (12) to any post treatment steps.

公开(公告)号：WO2007089223A3

公开(公告)日：2007-11-01

申请号：PCT/US2006001154

申请日：2006-01-12

Applicant: IBM ,  DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

Inventor： DIMITRAKOPOULOS CHRISTOS D ,  GATES STEPHEN M ,  GRILL ALFRED ,  LANE MICHAEL W ,  LINIGER ERIC G ,  LIU XIAO HU ,  NGUYEN SON VAN ,  NEUMAYER DEBORAH A ,  SHAW THOMAS M

IPC: H01L21/20 ,  B05C11/00 ,  B32B3/26

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract translation: 描述了一种用于形成具有受控双轴应力的超低介电常数层的方法，其包括通过PECVD和旋涂涂覆之一形成含有Si，C，O和H的层并且在包含非常低浓度 的氧气和水每个小于10ppm。 还通过使用介电常数不超过2.8的方法来描述材料。 本发明克服了形成低双轴应力小于46MPa的薄膜的问题。

公开(公告)号：WO2007089223A2

公开(公告)日：2007-08-09

申请号：PCT/US2006/001154

申请日：2006-01-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DIMITRAKOPOULOS, Christos, D. ,  GATES, Stephen, M. ,  GRILL, Alfred ,  LANE, Michael, W. ,  LINIGER, Eric, G. ,  LIU, Xiao, Hu ,  NGUYEN, Son, Van ,  NEUMAYER, Deborah, A. ,  SHAW, Thomas, M.

Inventor： DIMITRAKOPOULOS, Christos, D. ,  GATES, Stephen, M. ,  GRILL, Alfred ,  LANE, Michael, W. ,  LINIGER, Eric, G. ,  LIU, Xiao, Hu ,  NGUYEN, Son, Van ,  NEUMAYER, Deborah, A. ,  SHAW, Thomas, M.

IPC: H01L21/00

CPC classification number: H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

Abstract: A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

Abstract translation: 描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜 的氧和水各自小于10ppm。 还通过使用介电常数不大于2.8的方法描述材料。 本发明克服了低双轴应力低于46MPa的薄膜形成问题。

公开(公告)号：WO2006096813A2

公开(公告)日：2006-09-14

申请号：PCT/US2006008449

申请日：2006-03-08

Applicant: IBM ,  SONY CORP ,  NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

Inventor： NGUYEN SON V ,  LANE SARAH L ,  LINIGER ERIC G ,  IDA KENSAKU ,  RESTAINO DARRYL D

IPC: H01L21/469 ,  H01L23/52 ,  H01L23/58

CPC classification number: H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A material stack (12) is provided comprising one or more films (14) that have a crack velocity of about IE- 10 m/sec or greater and at least one monolayer (16) within or in direct contact with the one or more films (14), wherein the at least one monolayer (16) reduces the crack velocity of the material stack (12) to a value of less than lE-10 m/sec. The one or more films ( 14) are not limited to low k dielectrics, but may include materials such as a metal. In a preferred embodiment, a low k dielectric stack (12) is provided, having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack (12) are improved by introducing at least one nanolayer (16) into the dielectric stack (12). The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of me films within the stack (12) and without the need of subjecting the inventive dielectric stack (12) to any post treatment steps.

Abstract translation: 提供材料堆叠（12），其包括一个或多个膜（14），其具有大约IE-10m / sec或更大的裂纹速度和至少一个单层（16）在一个或多个膜内或直接接触一个或多个膜 （14），其中所述至少一个单层（16）将所述材料堆叠（12）的裂纹速度降低到小于1E-10m / sec的值。 一个或多个膜（14）不限于低k电介质，而是可以包括诸如金属的材料。 在优选实施例中，提供具有约3.0或更小的有效介电常数k的低k电介质堆叠（12），其中通过引入至少一个纳米层（16）来提高堆叠（12）的机械性能 ）到介电叠层（12）中。 在不显着增加叠层（12）内的薄膜的介电常数并且不需要对本发明的电介质叠层（12）进行任何后处理步骤的情况下，实现机械性能的改善。

公开(公告)号：WO2004042817A1

公开(公告)日：2004-05-21

申请号：PCT/US2002/035116

申请日：2002-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FITZSIMMONS, John, A. ,  GATES, Stephen, M. ,  LANE, Michael, W. ,  LINIGER, Eric, G.

Inventor： FITZSIMMONS, John, A. ,  GATES, Stephen, M. ,  LANE, Michael, W. ,  LINIGER, Eric, G.

IPC: H01L23/12

CPC classification number: H01L24/05 ,  H01L23/296 ,  H01L23/3135 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/48463 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01054 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/30105 ,  H01L2224/45099

Abstract: A method is disclosed of repairing wirebond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-k dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/ humiditylbias (THB) performance of such semiconductor devices.

Abstract translation: 公开了一种修复半导体芯片（例如高速半导体微处理器，专用集成电路（ASIC））和其它高速集成电路器件（特别是使用低k电介质材料的器件）的引线键合损坏的方法。 该方法涉及使用反应性液体的表面改性。 在优选的实施方案中，该方法包括将诸如TEOS的含硅液体试剂前体施加到芯片的表面，并允许液体试剂与水分反应形成固体电介质塞或膜（50）以产生抵抗 水分进入，从而提高这种半导体器件的温度/湿度（THB）性能。