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    IMPROVED SENSITIVITY CAPACITIVE SENSOR
    1.
    发明申请
    IMPROVED SENSITIVITY CAPACITIVE SENSOR 审中-公开
    改进的灵敏度电容式传感器

    公开(公告)号：WO2008085771A2

    公开(公告)日：2008-07-17

    申请号：PCT/US2007/089051

    申请日：2007-12-28

    Applicant: CUBIC WAFER, INC. ,  MISRA, Abhay ,  TREZZA, John

    Inventor： MISRA, Abhay ,  TREZZA, John

    IPC: H01L21/82 ,  G01R27/26

    CPC classification number: G06K9/0002 ,  H01L2224/48091 ,  H01L2224/8592 ,  Y10T29/49002 ,  Y10T29/49007 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00014

    Abstract: A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electronically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25μm. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less that 25μm.

    Abstract translation: 创建改进的灵敏度电容式指纹传感器的方法包括从具有电容传感器阵列的传感器芯片的第一侧形成通孔，使得通孔电子地导电，并且将覆盖板附接在传感器芯片的与第 传感器芯片距离小于25μm。 改进的灵敏度电容式指纹传感器具有电容式传感器阵列，其包括多个传感器单元和从用于传感器单元电路的连接点延伸到电容式传感器阵列背面的导电的通孔，包括主动检测电路和电连接 点，电连接点分别连接到相应的传感器单元电路连接点，以及盖板，以小于25μm的间隔设置在传感器单元之上。

    CMOS POWER AMPLIFIERS HAVING INTEGRATED ONE-TIME PROGRAMMABLE (OTP) MEMORIES
    2.
    发明申请
    CMOS POWER AMPLIFIERS HAVING INTEGRATED ONE-TIME PROGRAMMABLE (OTP) MEMORIES 审中-公开
    CMOS功率放大器具有集成的一次性可编程（OTP）存储器

    公开(公告)号：WO2011093996A3

    公开(公告)日：2011-08-04

    申请号：PCT/US2011/000135

    申请日：2011-01-25

    Applicant: JAVELIN SEMICONDUCTOR, INC. ,  DUPUIS, Timothy, J. ,  MISRA, Abhay

    Inventor： DUPUIS, Timothy, J. ,  MISRA, Abhay

    IPC: H03F1/22 ,  H03F3/20

    Abstract: CMOS power amplifiers (PAs) are disclosed having one or more integrated one-time programming (OTP) memories that are utilized to control at least in part operation of the CMOS PAs. The integrated OTP memories within the CMOS power amplifiers (PAs) allow adjustments, such as one-time factory trimming, of CMOS PA integrated circuits to optimize or improve performance. With this capability, for example, the tuning and biasing of stages within a multi-stage amplifier within a CMOS PA can be measured during factory test and adjusted by setting one or more bits in the OTP memories, as desired. Further, the operation of other circuitry within the PA can also be controlled at least in part with parameter settings stored in the OTP memories.

    Abstract translation: 所公开的CMOS功率放大器（PA）具有一个或多个集成的一次编程（OTP）存储器，其被用来至少部分地控制CMOS PA的操作。 CMOS功率放大器（PA）内的集成OTP存储器允许对CMOS PA集成电路进行调整，例如一次性工厂调整，以优化或提高性能。 例如，通过这种功能，可以在工厂测试期间测量CMOS PA内多级放大器内的级的调谐和偏置，并根据需要通过在OTP存储器中设置一个或多个位来进行调节。 此外，PA内的其他电路的操作也可以至少部分地通过存储在OTP存储器中的参数设置来控制。

    IMPROVED SENSITIVITY CAPACITIVE SENSOR
    3.
    发明申请
    IMPROVED SENSITIVITY CAPACITIVE SENSOR 审中-公开
    改进的灵敏度电容式传感器

    公开(公告)号：WO2008085771A3

    公开(公告)日：2008-12-18

    申请号：PCT/US2007089051

    申请日：2007-12-28

    Applicant: CUFER ASSET LTD LLC ,  MISRA ABHAY ,  TREZZA JOHN

    Inventor： MISRA ABHAY ,  TREZZA JOHN

    IPC: G01R27/26

    CPC classification number: G06K9/0002 ,  H01L2224/48091 ,  H01L2224/8592 ,  Y10T29/49002 ,  Y10T29/49007 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00014

    Abstract: A method of creating an improved sensitivity capacitive fingerprint sensor involves forming vias from a first side of a sensor chip having an array of capacitive sensors, making the vias electronically conductive, and attaching a cover plate over the first side of the sensor chip spaced from the sensor chip by a distance of less than 25µm. An improved sensitivity capacitive fingerprint sensor has a capacitive sensor array including multiple sensor cells and electrically conductive, through-chip vias extending from connection points for sensor cell circuitry to a back side of the capacitive sensor array, a chip including active detection circuitry and electrical connection points, the electrical connection points being respectively connected to corresponding ones of the sensor cell circuitry connection points, and a cover plate, disposed above the sensor cells at a spacing of less that 25µm.

    Abstract translation: 一种创建改进的灵敏度电容式指纹传感器的方法涉及从具有电容传感器阵列的传感器芯片的第一侧形成通孔，使通孔电子地导电，并且将传感器芯片的第一侧上的盖板附接到传感器芯片的第一侧 传感器芯片的距离小于25μm。 改进的灵敏度电容式指纹传感器具有电容式传感器阵列，其包括多个传感器单元以及从用于传感器单元电路的连接点延伸到电容式传感器阵列的背侧的导电的贯穿芯片通孔，芯片包括有源检测电路和电连接 电连接点分别连接到相应的传感器单元电路连接点，以及盖板，以小于25μm的间距设置在传感器单元上​​方。

    ROUTINGLESS CHIP ARCHITECTURE
    5.
    发明申请
    ROUTINGLESS CHIP ARCHITECTURE 审中-公开

    公开(公告)号：WO2006138490A3

    公开(公告)日：2006-12-28

    申请号：PCT/US2006/023362

    申请日：2006-06-14

    Applicant: CUBIC WAFER, INC. ,  TREZZA, John ,  MISRA, Abhay

    Inventor： TREZZA, John ,  MISRA, Abhay

    IPC: H01L21/44

    Abstract: A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back- end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the multiple devices to each other, and bonding the first wafer to the second wafer such that the multiple devices on the first wafer are interconnected to each other by the metal traces of the second wafer.

    CMOS POWER AMPLIFIERS HAVING INTEGRATED ONE-TIME PROGRAMMABLE (OTP) MEMORIES
    6.
    发明申请
    CMOS POWER AMPLIFIERS HAVING INTEGRATED ONE-TIME PROGRAMMABLE (OTP) MEMORIES 审中-公开
    具有集成的一次性可编程（OTP）存储器的CMOS功率放大器

    公开(公告)号：WO2011093996A2

    公开(公告)日：2011-08-04

    申请号：PCT/US2011000135

    申请日：2011-01-25

    Applicant: JAVELIN SEMICONDUCTOR INC ,  DUPUIS TIMOTHY J ,  MISRA ABHAY

    Inventor： DUPUIS TIMOTHY J ,  MISRA ABHAY

    IPC: H03F1/22 ,  H03F3/20

    CPC classification number: H03F3/24 ,  H03F1/0261 ,  H03F3/195 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/408 ,  H03F2200/451

    Abstract: CMOS power amplifiers (PAs) are disclosed having one or more integrated one-time programming (OTP) memories that are utilized to control at least in part operation of the CMOS PAs. The integrated OTP memories within the CMOS power amplifiers (PAs) allow adjustments, such as one-time factory trimming, of CMOS PA integrated circuits to optimize or improve performance. With this capability, for example, the tuning and biasing of stages within a multi-stage amplifier within a CMOS PA can be measured during factory test and adjusted by setting one or more bits in the OTP memories, as desired. Further, the operation of other circuitry within the PA can also be controlled at least in part with parameter settings stored in the OTP memories.

    Abstract translation: 公开了具有一个或多个集成的一次编程（OTP）存储器的CMOS功率放大器（PA），其用于至少部分地控制CMOS PA的工作。 CMOS功率放大器（PA）内的集成OTP存储器允许调整CMOS PA集成电路的一次性工厂调整，以优化或提高性能。 例如，通过这种能力，可以在工厂测试期间测量CMOS PA内的多级放大器中的级的调谐和偏置，并根据需要通过设置OTP存储器中的一个或多个位来进行调整。 此外，还可以至少部分地通过存储在OTP存储器中的参数设置来控制PA内的其它电路的操作。

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