公开(公告)号：WO2006138424A3

公开(公告)日：2009-06-04

申请号：PCT/US2006023248

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TRZZA JOHN

Inventor： TRZZA JOHN

IPC: H01L21/31

CPC classification number: H01L21/76898 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of forming an electrically conductive path through a portion of a semiconductor material, wherein the semiconductor material abuts a substrate and wherein the semiconductor material comprises multiple electronic devices, involves forming an annular trench in the portion, forming an island of semiconductor material within the annular trench, filling the annular trench with an electrically insulating material, removing at least some of the island of semiconductor material to create an exposed inner surface, metalizing at least a portion of the exposed inner surface with a material, and thinning an outer surface side of the substrate until at least the material from the metalizing is exposed on the outer surface side of the substrate.

Abstract translation: 一种通过半导体材料的一部分形成导电路径的方法，其中所述半导体材料邻接衬底，并且其中所述半导体材料包括多个电子器件，包括在所述部分中形成环形沟槽，在所述半导体材料的内部形成半导体材料岛 环形沟槽，用电绝缘材料填充环形沟槽，去除半导体材料岛中的至少一些以产生暴露的内表面，用材料金属化暴露的内表面的至少一部分，并使外表面侧变薄 直到至少来自金属化的材料暴露在基板的外表面侧上。

公开(公告)号：WO2006138496A3

公开(公告)日：2009-05-07

申请号：PCT/US2006023368

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN

Inventor： TREZZA JOHN

IPC: H01L21/44

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/75 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of attaching a pair of chips (a and b) shown in Figure (150), each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of the corresponding primary contacts of each of the chips in the pair forms an electrical connection

Abstract translation: 附接图150所示的一对芯片（a和b）的方法，每个芯片（150）具有可彼此配合的初级触点，包括在两个芯片中的每一个上形成一个或多个二次触点， 防止在初步附接操作期间初始附接材料接触任何主触头，次级触点进一步具有一高度，当二次触点彼此接触时，该高度将防止主触头接触，使次触点进入 至少直到初级触点接触第一阶段并且加热初级触点，直到该对中的每个芯片的每个相应的初级触点之间的材料形成电连接

公开(公告)号：WO2006138425A3

公开(公告)日：2007-08-16

申请号：PCT/US2006023249

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN

Inventor： TREZZA JOHN

IPC: H01L23/52

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A system has a first chip having first semiconductor devices and first electrical connections, a second chip having second semiconductor devices and second electrical connections, and a third chip having third semiconductor devices and third electrical connections, the third chip being stacked on top of and physically spanning at least a portion of each of the first and second chips and being connected to the first and second chips.

Abstract translation: 系统具有具有第一半导体器件和第一电连接的第一芯片，具有第二半导体器件和第二电连接的第二芯片，以及具有第三半导体器件和第三电连接的第三芯片，第三芯片堆叠在物理的顶部 跨越第一和第二芯片中的每一个的至少一部分并连接到第一和第二芯片。

公开(公告)号：WO2006138492A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023364

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  TREZZA, John ,  CALLAHAN, John ,  DUDOFF, Gregory

Inventor： TREZZA, John ,  CALLAHAN, John ,  DUDOFF, Gregory

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2223/6622 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/274 ,  H01L2224/75305 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/0014 ,  H01S5/0201 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of physically and electrically joining two chips to each other involves aligning an electrically conductive contact of a first chip with a corresponding electrically conductive contact on a second chip, the electrically conductive contact of the first chip being a rigid material and the electrically conductive contact of the second chip being a material that is malleable, bringing the aligned electrically conductive contact of the first chip into contact with the corresponding electrically conductive contact on the second chip, elevating the contact of the chips to a temperature that is below a liquidus temperature for both the rigid material and the material that is malleable while applying pressure to the chips so as to cause the rigid material to penetrate the malleable material and form an electrically conductive connection, and, following the forming of the electrically conductive connection, cooling the contacts to an ambient temperature.

Abstract translation: 将两个芯片彼此物理和电连接的方法包括将第一芯片的导电触点与第二芯片上的对应导电触点对准，第一芯片的导电触点是刚性材料，并且导电触点 第二芯片是具有延展性的材料，使得第一芯片的对齐的导电触点与第二芯片上的对应的导电触点接触，将芯片的接触升高到低于液相线温度的温度 刚性材料和材料都是可塑的，同时向芯片施加压力，以使刚性材料穿透可延展材料并形成导电连接，并且在形成导电连接之后，将触点冷却 环境温度。

公开(公告)号：WO2006138491A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023363

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  TREZZA, John

Inventor： TREZZA, John

IPC: H01L23/48

CPC classification number: H01L24/94 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/274 ,  H01L2224/75305 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.

Abstract translation: 在具有邻接衬底的掺杂半导体材料的半导体芯片上执行的方法包括通过从衬底的外侧向掺杂半导体材料延伸的至少部分衬底形成第一通孔，第一通孔具有壁表面和 将第一导电材料引入第一通孔中以形成导电路径，从半导体芯片的掺杂部分的外表面延伸到底部，产生与第一通孔对准的第二通孔， 并将第二导电材料引入第二通孔中，以便产生导电路径。

公开(公告)号：WO2006138457A2

公开(公告)日：2006-12-28

申请号：PCT/US2006/023297

申请日：2006-06-14

Applicant: CUBIC WAFER, INC. ,  TREZZA, John

Inventor： TREZZA, John

IPC: H01L23/48

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6616 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/75305 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T428/24174 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area.

Abstract translation: 一种装置具有彼此连接的两块基板材料，两个板包括彼此连接的一对触点，该一对触点具有将第一区域与第二区域分开的形状。

公开(公告)号：WO2018215524A1

公开(公告)日：2018-11-29

申请号：PCT/EP2018/063475

申请日：2018-05-23

Applicant: DANFOSS SILICON POWER GMBH

Inventor： PAULSEN, Lars ,  ULRICH, Holger ,  OSTERWALD, Frank ,  RUDZKI, Jacek ,  BECKER, Martin ,  DITTMANN, Dirk

IPC: H01L21/67

CPC classification number: H01L24/75 ,  H01L2224/751 ,  H01L2224/75305 ,  H01L2224/75316 ,  H01L2224/75317 ,  H01L2224/75318 ,  H01L2224/7532 ,  H01L2224/75983 ,  H01L2224/83065 ,  H01L2224/83093 ,  H01L2224/83201 ,  H01L2224/8384 ,  H01L2924/00012

Abstract: An assembly for producing an electronic assembly by sintering, comprising a lower sintering tool (30) having a recess (32) for receiving an electronic assembly (20) to be produced by sintering, an upper sintering tool (40) for exerting a pressure directed against the lower sintering tool, and a protective film (50) arranged between the lower sintering tool and the upper sintering tool covering at least the recess of the lower sintering tool, characterized in that the protective film is perforated (52) to allow the feeding of a protective gas to the surface of the electronic assembly (20).

公开(公告)号：WO2016157464A1

公开(公告)日：2016-10-06

申请号：PCT/JP2015/060296

申请日：2015-03-31

Applicant: 新電元工業株式会社

Inventor： 松林　良

IPC: H01L21/52

CPC classification number: H01L24/75 ,  B23K1/0016 ,  B23K20/023 ,  B23K20/233 ,  B23K2201/42 ,  H01L21/52 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/75252 ,  H01L2224/75305 ,  H01L2224/75312 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75824 ,  H01L2224/83203

Abstract: 　基板１に金属粒子ペースト４を介して電子部品２を配置した組立体２０を加圧及び加熱して金属粒子ペースト４を焼成する際に用い、金属粒子ペースト４を焼成する際に組立体を挟み込む板状の伝達部材であって、伝達部材１１０，１２０は、熱伝導率が１～２００Ｗ／（ｍ・Ｋ）の範囲内にあり、かつ、ビッカース硬さが１８０～２３００ｋｇｆ／ｍｍ ２ の範囲内にある材料からなることを特徴とする伝達部材１１０，１２０。　本発明の伝達部材は、基板と電子部品との接合性が低下するのを抑制することが可能であり、かつ、接合体の生産効率が著しく低下してしまうのを防止することが可能な接合体の製造方法に用いるための伝達部材となる。

Abstract translation: 公开了在加压和加热其中电子部件2布置在基板1上的金属颗粒糊4并烧制金属颗粒浆料4的组件20时使用的板状传动部件110,120， 在烧制金属颗粒糊料4时夹持组件的传动构件，其中每个传动构件110,120由导热率为1至200W /（m·K）的材料制成，并且 维氏硬度范围为180至2300 kgf / mm2。 这些传输部件用于能够抑制基板和电子部件之间的接合性降低的粘合体的制造方法，能够防止粘接体的生产效率显着降低。

公开(公告)号：WO2016036874A1

公开(公告)日：2016-03-10

申请号：PCT/US2015/048176

申请日：2015-09-02

Applicant: SKORPIOS TECHNOLOGIES, INC.

Inventor： LAMBERT, Damien ,  SPANN, John ,  KRASULICK, Stephen

IPC: H01L21/60

CPC classification number: H01L21/6835 ,  G02B6/4201 ,  H01L21/0274 ,  H01L21/2007 ,  H01L21/683 ,  H01L21/76254 ,  H01L24/03 ,  H01L24/27 ,  H01L24/75 ,  H01L24/83 ,  H01L24/89 ,  H01L24/94 ,  H01L24/95 ,  H01L2221/68313 ,  H01L2221/68318 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/0362 ,  H01L2224/75305 ,  H01L2224/75315 ,  H01L2224/80201 ,  H01L2224/83001 ,  H01L2224/83203 ,  H01L2225/06593 ,  H01L2924/01014 ,  H01L2924/1032 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/15738

Abstract: A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light.

Abstract translation: 使用具有顺应性树脂的转印衬底将一个或多个芯片结合到目标晶片。 植入区域形成在转印衬底中。 转印衬底的一部分被蚀刻以形成提升器。 将合适的材料施加到转印基板上。 芯片被固定到柔性材料上，其中芯片被固定到提升管上方的柔性材料。 当芯片固定到顺应性材料时，芯片被结合到目标晶片。 从芯片上去除转印衬底和柔顺材料。 转印衬底对UV光是不透明的。

公开(公告)号：WO2015137029A1

公开(公告)日：2015-09-17

申请号：PCT/JP2015/053590

申请日：2015-02-10

Applicant: 株式会社新川

Inventor： 坂本　光輝 ,  久保　晶義

IPC: H01L21/52 ,  H01L21/60

CPC classification number: H01L24/75 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/78 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/751 ,  H01L2224/75251 ,  H01L2224/75305 ,  H01L2224/7531 ,  H01L2224/75651 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/759 ,  H01L2224/781 ,  H01L2224/78251 ,  H01L2224/78304 ,  H01L2224/78307 ,  H01L2224/78651 ,  H01L2224/78702 ,  H01L2224/78753 ,  H01L2224/78824 ,  H01L2224/789 ,  H01L2224/81065 ,  H01L2224/81075 ,  H01L2224/81093 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/83093 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85093 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: 本実施形態に係るボンディング装置は、搬送部（２０）に形成されているボンディング用開口（２６）からボンディング対象を認識するための撮影空間（ＶＳ）を横切るように第１の気体流（Ｄ１）を形成する第１のブロワー部（１１ｈ）と、撮影空間に沿って第２の気体流（Ｄ２）を形成する第２のブロワー部（１２ｈ）とを備える。第２のブロワー部（１２ｈ）は、第１の気体流（Ｄ１）によって周囲の気体（Ｇ２）が撮影空間（ＶＳ）に巻き込まれることを抑制するように第２の気体流（Ｄ２）による障壁を形成する。これにより、基板やリードフレーム等のボンディング対象物を加熱することによって生じる陽炎の影響を抑制することができる。

Abstract translation: 根据本发明的实施例，粘合装置具有：形成第一气流（D1）的第一鼓风机部分（11h），使得第一气流跨越拍摄空间（VS），以从 形成在转印部（20）中的接合开口（26），要接合的对象; 以及沿着拍摄空间形成第二气流（D2）的第二鼓风机部分（12h）。 第二送风部（12h）借助于第二气流（D2）形成阻挡壁，以便抑制由于第一气流（D1）而将周围气体（G2）进入拍摄空间（VS）。 因此，可以抑制加热对象（例如基板和引线框架）时产生的热雾的影响。