公开(公告)号：WO2006138495A3

公开(公告)日：2009-05-07

申请号：PCT/US2006023367

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN ,  MISRA ABHAY

Inventor： TREZZA JOHN ,  MISRA ABHAY

IPC: H01L27/00

CPC classification number: H01L25/18 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method involves stacking a first chip, comprising high-speed circuitry formed using a first fabrication process, together with a wafer comprising multiple iterations of low-speed circuitry formed using a second fabrication process, hybridizing the first chip to the wafer so as to form electrical connections between the first chip and one of the iterations of the low-speed circuitry so as to form a hybridized unit and dicing the unit from the wafer.

Abstract translation: 一种方法包括堆叠第一芯片，包括使用第一制造工艺形成的高速电路，以及包括使用第二制造工艺形成的多次迭代的低速电路的晶片，将第一芯片与晶片杂交以形成 第一芯片之间的电连接和低速电路的迭代之一，以形成混合单元并从晶片切割单元。

公开(公告)号：WO2006138490A2

公开(公告)日：2006-12-28

申请号：PCT/US2006023362

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN ,  MISRA ABHAY

Inventor： TREZZA JOHN ,  MISRA ABHAY

IPC: H01L21/4763

CPC classification number: H01L21/76898 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/24 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back- end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the multiple devices to each other, and bonding the first wafer to the second wafer such that the multiple devices on the first wafer are interconnected to each other by the metal traces of the second wafer.

Abstract translation: 创建统一芯片的方法涉及在第一晶片上进行前端处理，前端处理在晶片上创建多个器件，在第二晶片上执行后端处理，后端处理产生互连的金属迹线层，布置 将所述多个设备中的至少一些彼此互连，以及将所述第一晶片接合到所述第二晶片，使得所述第一晶片上的所述多个器件通过所述第二晶片的金属迹线彼此互连。

公开(公告)号：WO2006138381A3

公开(公告)日：2008-11-20

申请号：PCT/US2006023174

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN ,  CALLAHAN JOHN ,  DUDOFF GREGORY

Inventor： TREZZA JOHN ,  CALLAHAN JOHN ,  DUDOFF GREGORY

IPC: H01L21/44 ,  A47J36/02 ,  B23K31/00 ,  B23K31/02 ,  B23K31/12 ,  H01L21/30 ,  H01L21/46 ,  H01L21/50 ,  H05K3/34

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of joining contacts on two chips (4706, 4708), each having multiple contacts (4702, 4704), to each other involves maintaining a first of the chips at a first temperature, the first of the chips having a rigid electrical contact (4704) thereon, bringing a second chip, having an electrical contact (4702) that is malleable with respect to the rigid contact and matingly corresponding thereto, into contact with the first such that the corresponding rigid and malleable contact are brought together, locally raising the second of the chips to a local temperatur that is sufficiently high to cause material of the rigid and malleable contact to interdiffuse, interpenetrate or both, but below both a temperature that would cause the material to become liquidus and a fuse temperature, and allowing the second of the chips to cool to at least the first temperature.

Abstract translation: 在两个彼此具有多个触点（4702,4704）的芯片（4706,4708）上接合触点的方法涉及将第一芯片保持在第一温度，第一芯片具有刚性电接触（ 4704），使具有相对于刚性接触件并且与之对应的电触头（4702）与第一芯片接触的第二芯片与第一芯片接触，使得相应的刚性和可延展的触点被集合在一起， 芯片中的第二芯片达到足够高的局部温度，以使刚性和可延展的接触材料相互扩散，互穿或两者都相互渗透，但低于导致材料变成液相线的温度和熔丝温度，并允许第二 的芯片至少冷却至第一温度。

公开(公告)号：WO2008101093B1

公开(公告)日：2008-10-30

申请号：PCT/US2008053982

申请日：2008-02-14

Applicant: CUBIC WAFER INC ,  CALLAHAN JOHN ,  TREZZA JOHN

Inventor： CALLAHAN JOHN ,  TREZZA JOHN

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above the seed layer that is at least equal to a thickness of the seed layer, removing the solid photoresist, and removing seed layer exposed by removal of the phototresist and plated metal until all of the exposed seed layer has been removed.

Abstract translation: 一种方法包括图案蚀刻位于晶片上的光致抗蚀剂，该光致抗蚀剂包含沉积的种子层以暴露种子层的部分，电镀晶片，使得电镀金属仅在暴露的种子层上积累，直到电镀金属达到高度 在晶种层上方至少等于种子层的厚度，去除固体光致抗蚀剂，以及通过除去光致抗蚀剂和电镀金属去除暴露的种子层，直到所有暴露的种子层已被去除。

公开(公告)号：WO2006138491A3

公开(公告)日：2009-05-07

申请号：PCT/US2006023363

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN

Inventor： TREZZA JOHN

IPC: H01L21/4763

CPC classification number: H01L24/94 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68368 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/274 ,  H01L2224/75305 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.

Abstract translation: 在具有邻接衬底的掺杂半导体材料的半导体芯片上执行的方法包括通过从衬底的外侧向掺杂半导体材料延伸的至少部分衬底形成第一通孔，第一通孔具有壁表面和 将第一导电材料引入第一通孔中以形成导电路径，从半导体芯片的掺杂部分的外表面延伸到底部，产生与第一通孔对准的第二通孔， 并将第二导电材料引入第二通孔中，以便产生导电路径。

公开(公告)号：WO2006138494A3

公开(公告)日：2007-03-22

申请号：PCT/US2006023366

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN

Inventor： TREZZA JOHN

IPC: H01L29/40

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/1358 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.

Abstract translation: 一种制造半导体芯片的方法，该半导体芯片具有衬底，与衬底相邻的掺杂半导体材料和在掺杂半导体材料的外侧的器件焊盘，包括通过衬底的至少一部分形成通孔，该通孔具有外围和 在足够的位置和深度处的底部，以使通孔靠近设备衬垫，但是物理地与器件衬垫隔开，将导电材料引入通孔，并将导电材料连接到信号源，使得信号 将有意地从导电材料传播到器件焊盘，而不会在导电材料和器件焊盘之间存在任何直接的电连接。

公开(公告)号：WO2006138423A2

公开(公告)日：2006-12-28

申请号：PCT/US2006023246

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN ,  CALLAHAN JOHN ,  DUDOFF GREGORY

Inventor： TREZZA JOHN ,  CALLAHAN JOHN ,  DUDOFF GREGORY

IPC: H01L23/52

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6616 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/75305 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of electrically joining a first contact on a first wafer with a second contact on a second wafer, the first contact, a rigid material, and the second contact, a material that is malleable relative to the rigid material, such that when brought together the rigid material will penetrate the malleable material, the rigid and malleable materials both being electrically conductive involves bringing the rigid material into contact with the malleable material, applying a force to one of the first contact or the second contact so as to cause the rigid material to penetrate the malleable material, heating the rigid and malleable material so as to cause the malleable material to soften, and constraining the malleable material to within a pre-specified area.

Abstract translation: 一种将第一晶片上的第一触点与第二晶片上的第二触点电连接的方法，所述第一触点，刚性材料和所述第二触点，相对于所述刚性材料是可延展的材料，使得当被连接在一起时 刚性材料将穿透可延展材料，刚性和可延展材料都是导电的，包括使刚性材料与可延展材料接触，向第一接触件或第二接触件中的一个施加力，从而使刚性材料 穿透可延展材料，加热刚性和有韧性的材料，以使有韧性的材料软化，并将可延展材料限制在预先指定的区域内。

公开(公告)号：WO2006138492A3

公开(公告)日：2007-03-29

申请号：PCT/US2006023364

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN ,  CALLAHAN JOHN ,  DUDOFF GREGORY

Inventor： TREZZA JOHN ,  CALLAHAN JOHN ,  DUDOFF GREGORY

IPC: H01L21/00

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/24 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2223/6622 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/274 ,  H01L2224/75305 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/0014 ,  H01S5/0201 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of physically and electrically joining two chips to each other involves aligning an electrically conductive contact of a first chip with a corresponding electrically conductive contact on a second chip, the electrically conductive contact of the first chip being a rigid material and the electrically conductive contact of the second chip being a material that is malleable, bringing the aligned electrically conductive contact of the first chip into contact with the corresponding electrically conductive contact on the second chip, elevating the contact of the chips to a temperature that is below a liquidus temperature for both the rigid material and the material that is malleable while applying pressure to the chips so as to cause the rigid material to penetrate the malleable material and form an electrically conductive connection, and, following the forming of the electrically conductive connection, cooling the contacts to an ambient temperature.

Abstract translation: 将两个芯片彼此物理和电连接的方法包括将第一芯片的导电触点与第二芯片上的对应导电触点对准，第一芯片的导电触点是刚性材料，并且导电触点 第二芯片是具有延展性的材料，使得第一芯片的对齐的导电触点与第二芯片上的对应的导电触点接触，将芯片的接触升高到低于液相线温度的温度 刚性材料和材料都是可塑的，同时向芯片施加压力，以使刚性材料穿透可延展材料并形成导电连接，并且在形成导电连接之后，将触点冷却 环境温度。

公开(公告)号：WO2006138457A3

公开(公告)日：2007-02-22

申请号：PCT/US2006023297

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  TREZZA JOHN

Inventor： TREZZA JOHN

IPC: H01L23/12

CPC classification number: H01L21/6836 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/427 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6616 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/75305 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T428/24174 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area.

Abstract translation: 一种装置具有彼此连接的两块基板材料，两个板包括彼此连接的一对触点，该一对触点具有将第一区域与第二区域分开的形状。

公开(公告)号：WO2006138426A3

公开(公告)日：2008-07-24

申请号：PCT/US2006023250

申请日：2006-06-14

Applicant: CUBIC WAFER INC ,  CALLAHAN JON ,  TREZZA JOHN ,  DUDOFF GREGORY

Inventor： CALLAHAN JON ,  TREZZA JOHN ,  DUDOFF GREGORY

IPC: H01L23/34 ,  H01L23/48

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/48 ,  H01L23/481 ,  H01L24/11 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/75305 ,  H01L2224/75315 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip contact functionally having an IC pad, a barrier layer over the IC pad, and a malleable material over the barrier layer. An alternative chip contact functionally having an IC pad, a barrier layer over the IC pad, and a rigid material over the barrier layer.

Abstract translation: 芯片接触器在功能上具有IC焊盘，IC焊盘上的阻挡层，以及在阻挡层上方的可延展材料。 替代的芯片接触器在功能上具有IC焊盘，IC焊盘上的阻挡层以及阻挡层上的刚性材料。