公开(公告)号：WO2013009853A2

公开(公告)日：2013-01-17

申请号：PCT/US2012/046229

申请日：2012-07-11

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED ,  YOKOYA, Satoshi ,  SIMMONS-MATTHEWS, Margaret, Rose

Inventor： YOKOYA, Satoshi ,  SIMMONS-MATTHEWS, Margaret, Rose

IPC: H01L23/36

CPC classification number: H01L23/36 ,  H01L23/4006 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/73 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An electronic assembly (150) includes a workpiece (110), a through substrate via (TSV) die (120) including a substrate (105) and a plurality of TSVs (115), a topside (121) and a bottomside (122) having TSV connectors (113) thereon. The TSV die is attached to the workpiece with its topside on the workpiece. A heat spreader (130) having an inner open window (131) is on the bottomside of the TSV die. Bonding features (161) are coupled to the TSV connectors or include the TSV connectors themselves. The bonding features protrude from the inner open window to a height above a height of the top (132) of the heat spreader that allows a top die to be bonded thereto.

Abstract translation: 一种电子组件（150），包括工件（110），包括衬底（105）和多个TSV（115）的衬底通孔（TSV）管芯（120），顶侧 其上具有TSV连接器（113）的底侧（122）。 TSV模具以工件顶面贴在工件上。 具有内开窗（131）的散热器（130）位于TSV裸片的底部。 接合特征（161）耦合到TSV连接器或者包括TSV连接器本身。 结合特征从内部开口窗突出到高于散热器顶部（132）高度的高度，其允许顶部管芯结合到其上。

公开(公告)号：WO2012040215A3

公开(公告)日：2012-06-14

申请号：PCT/US2011052376

申请日：2011-09-20

Applicant: TEXAS INSTRUMENTS INC ,  TEXAS INSTRUMENTS JAPAN ,  DUNNE RAJIV ,  SIMMONS-MATTHEWS MARGARET ROSE

Inventor： DUNNE RAJIV ,  SIMMONS-MATTHEWS MARGARET ROSE

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01043 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method (100) of through-substrate via (TSV) die assembly includes positioning (101) a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured (102) after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded (103) onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding (104) after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated (105) to form a plurality of singulated stacked die assemblies.

Abstract translation: 贯通衬底通孔（TSV）管芯组件的方法（100）包括将多个TSV管芯定位（101），其顶侧面向下面向载体上的可固化键合粘合剂层。 多个TSV管芯包括可接触TSV，其包括或连接到从其底部突出的可粘结底部特征。 定位后，可固化的粘合粘合剂层被固化（102）。 每个具有多个第二接合部件的多个第二IC管芯被接合（103）到多个TSV管芯上以在载体上形成多个堆叠的管芯组件。 粘合之后的剥离（104）将载体与多个堆叠的模具组件分离。 然后将多个堆叠的管芯组件分割（105）以形成多个经单个化的堆叠管芯组件。

公开(公告)号：WO2012040215A2

公开(公告)日：2012-03-29

申请号：PCT/US2011/052376

申请日：2011-09-20

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED ,  DUNNE, Rajiv ,  SIMMONS-MATTHEWS, Margaret, Rose

Inventor： DUNNE, Rajiv ,  SIMMONS-MATTHEWS, Margaret, Rose

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01043 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method (100) of through-substrate via (TSV) die assembly includes positioning (101) a plurality of TSV die with their topside facing down onto a curable bonding adhesive layer on a carrier. The plurality of TSV die include contactable TSVs that include or are coupled to bondable bottomside features protruding from its bottomside. The curable bonding adhesive layer is cured (102) after the positioning. A plurality of second IC die each having a plurality of second bonding features are bonded (103) onto the plurality of TSV die to form a plurality of stacked die assemblies on the carrier. Debonding (104) after the bonding separates the carrier from the plurality of stacked die assemblies. The plurality of stacked die assemblies are then singulated (105) to form a plurality of singulated stacked die assemblies.

Abstract translation: 贯穿基板通孔（TSV）模具组件的方法（100）包括将其顶面朝下的多个TSV模具定位（101）到载体上的可固化粘合粘合剂层上。 多个TSV模具包括可接触的TSV，其包括或耦合到从其底部突出的可粘合的底部特征。 固化粘合层在定位后固化（102）。 多个具有多个第二接合特征的第二IC芯片被接合（103）到多个TSV管芯上，以在载体上形成多个堆叠的管芯组件。 在粘合之后的剥离（104）将载体与多个堆叠的模具组件分离。 然后将多个堆叠的模具组件分割（105）以形成多个单独堆叠的模具组件。

公开(公告)号：WO2013009853A3

公开(公告)日：2013-04-04

申请号：PCT/US2012046229

申请日：2012-07-11

Applicant: TEXAS INSTRUMENTS INC ,  TEXAS INSTRUMENTS JAPAN ,  YOKOYA SATOSHI ,  SIMMONS-MATTHEWS MARGARET ROSE

Inventor： YOKOYA SATOSHI ,  SIMMONS-MATTHEWS MARGARET ROSE

IPC: H01L23/36

CPC classification number: H01L23/36 ,  H01L23/4006 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/73 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An electronic assembly (150) includes a workpiece (110), a through substrate via (TSV) die (120) including a substrate (105) and a plurality of TSVs (115), a topside (121) and a bottomside (122) having TSV connectors (113) thereon. The TSV die is attached to the workpiece with its topside on the workpiece. A heat spreader (130) having an inner open window (131) is on the bottomside of the TSV die. Bonding features (161) are coupled to the TSV connectors or include the TSV connectors themselves. The bonding features protrude from the inner open window to a height above a height of the top (132) of the heat spreader that allows a top die to be bonded thereto.

Abstract translation: 电子组件（150）包括工件（110），包括衬底（105）和多个TSV（115）的贯穿衬底通孔（TSV）管芯（120），顶侧（121）和底部（122） 在其上具有TSV连接器（113）。 TSV模具在工件的上侧附着在工件上。 具有内部开放窗口（131）的散热器（130）位于TSV模具的底部。 接合特征（161）耦合到TSV连接器或包括TSV连接器本身。 结合特征从内部敞开的窗口突出到允许顶部模具结合到其上的散热器的顶部（132）的高度之上的高度。

公开(公告)号：WO2011140552A3

公开(公告)日：2012-03-01

申请号：PCT/US2011035753

申请日：2011-05-09

Applicant: TEXAS INSTRUMENTS INC ,  TEXAS INSTRUMENTS JAPAN ,  WACHTLER KURT ,  SIMMONS-MATTHEWS MARGARET ROSE

Inventor： WACHTLER KURT ,  SIMMONS-MATTHEWS MARGARET ROSE

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device (10) includes a first memory die (12) having a first memory type, a second memory die (14) having a second memory type different from the first memory type, and a logic die (16) such as a microprocessor. The first memory die (12) can be electrically connected to the logic die (16) using a first type of electrical connection preferred for the first memory type. The second memory die (14) can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.

Abstract translation: 半导体器件（10）包括具有第一存储器类型的第一存储器管芯（12），具有不同于第一存储器类型的第二存储器类型的第二存储器管芯（14），以及诸如微处理器 。 可以使用对于第一存储器类型优选的第一类型的电连接来将第一存储器管芯（12）电连接到逻辑管芯（16）。 第二存储器管芯（14）可以使用不同于第二存储器类型的第一类型电连接的第二类型的电连接而与逻辑管芯电连接。 其他装置可以包括相同类型的模具，或者具有第一类型的两个或更多个模具和不同于第一类型的第二类型的两个或更多个模具。

公开(公告)号：WO2011139875A2

公开(公告)日：2011-11-10

申请号：PCT/US2011/034444

申请日：2011-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED ,  SIMMONS-MATTHEWS, Margaret, Rose

Inventor： SIMMONS-MATTHEWS, Margaret, Rose

IPC: H01L23/48 ,  H01L23/34

CPC classification number: H01L23/49894 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A method (100) for assembling die packages includes attaching contacts (101) on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the coefficient of thermal expansion (CTE) mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed (103) from the package substrate. Electrically conductive connectors are attached (104) to the bottom surface of the package substrate, and the package substrate is sawed (105) to form a plurality of singulated die packages.

Abstract translation: 用于组装管芯封装的方法（100）包括将多个第一管芯的第一侧上的接触件（101）附接到复合载体的顶表面上的衬底焊盘。 复合载体包括包含至少一个嵌入金属层的封装衬底，其底表面固定在半导体晶片上。 复合载体最大限度地减少了在组装期间模头和封装衬底之间的热膨胀系数（CTE）失配的影响，从而减小了模具的翘曲。 在安装之后，半导体晶片从封装衬底移除（103）。 将电导体连接器（104）连接到封装基板的底表面，并且封装基板被锯（105）以形成多个分割的管芯封装。

公开(公告)号：WO2011139875A3

公开(公告)日：2012-02-23

申请号：PCT/US2011034444

申请日：2011-04-29

Applicant: TEXAS INSTRUMENTS INC ,  TEXAS INSTRUMENTS JAPAN ,  SIMMONS-MATTHEWS MARGARET ROSE

Inventor： SIMMONS-MATTHEWS MARGARET ROSE

IPC: H01L23/48 ,  H01L23/34

CPC classification number: H01L23/49894 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A method (100) for assembling die packages includes attaching contacts (101) on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the coefficient of thermal expansion (CTE) mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed (103) from the package substrate. Electrically conductive connectors are attached (104) to the bottom surface of the package substrate, and the package substrate is sawed (105) to form a plurality of singulated die packages.

Abstract translation: 用于组装管芯封装的方法（100）包括将多个第一管芯的第一侧上的接触件（101）附接到复合载体的顶表面上的衬底焊盘。 复合载体包括包含至少一个嵌入金属层的封装衬底，其底表面固定在半导体晶片上。 复合载体最大限度地减少了在组装期间模头和封装衬底之间的热膨胀系数（CTE）失配的影响，从而减小了模具的翘曲。 在安装之后，半导体晶片从封装衬底移除（103）。 将电导体连接器（104）连接到封装基板的底表面，并且封装基板被锯（105）以形成多个分割的管芯封装。

公开(公告)号：WO2011140552A2

公开(公告)日：2011-11-10

申请号：PCT/US2011/035753

申请日：2011-05-09

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED ,  WACHTLER, Kurt ,  SIMMONS-MATTHEWS, Margaret, Rose

Inventor： WACHTLER, Kurt ,  SIMMONS-MATTHEWS, Margaret, Rose

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device (10) includes a first memory die (12) having a first memory type, a second memory die (14) having a second memory type different from the first memory type, and a logic die (16) such as a microprocessor. The first memory die (12) can be electrically connected to the logic die (16) using a first type of electrical connection preferred for the first memory type. The second memory die (14) can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.

Abstract translation: 半导体器件（10）包括具有第一存储器类型的第一存储器管芯（12），具有不同于第一存储器类型的第二存储器类型的第二存储器管芯（14），以及诸如微处理器 。 可以使用对于第一存储器类型优选的第一类型的电连接来将第一存储器管芯（12）电连接到逻辑管芯（16）。 第二存储器管芯（14）可以使用不同于第二存储器类型的第一类型电连接的第二类型的电连接而与逻辑管芯电连接。 其他装置可以包括相同类型的模具，或者具有第一类型的两个或更多个模具和不同于第一类型的第二类型的两个或更多个模具。