公开(公告)号：WO2006035321A2

公开(公告)日：2006-04-06

申请号：PCT/IB2005/003992

申请日：2005-05-05

Applicant: UNITED TEST AND ASSEMBLY CENTER, LTD. ,  KOLAN, Ravi, Kanth ,  TAN, Hien, Boon ,  SUN, Yi-sheng, Anthony ,  KUAN, Lim, Beng ,  SHIVALINGAM, Krishnamurthy

Inventor： KOLAN, Ravi, Kanth ,  TAN, Hien, Boon ,  SUN, Yi-sheng, Anthony ,  KUAN, Lim, Beng ,  SHIVALINGAM, Krishnamurthy

CPC classification number: H01L21/566 ,  H01L23/3114 ,  H01L23/4334 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/19041 ,  H01L2224/13099 ,  H01L2924/013 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free form encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.

Abstract translation: 芯片级集成电​​路封装包括具有第一面和第二面的集成电路芯片。 在集成电路芯片的第一面上形成多个柱状凸块。 封装材料封装集成电路芯片的侧面和第一面以及柱状凸块。 柱状凸块的上端保持自由形式的密封剂材料，并且通过密封剂材料的上表面和柱状凸块的上端形成大致平坦的表面。 多个焊球安装在基本平坦的表面上对应于柱形凸块上端的位置上。

公开(公告)号：WO2004088727A2

公开(公告)日：2004-10-14

申请号：PCT/IB2004/001734

申请日：2004-04-02

Applicant: UNITED TEST AND ASSEMBLY CENTER LTD. ,  INFINEON, TECHNOLOGIES ,  LENG, Chen Fung ,  KWANG, Brandon, Kim, Seong ,  LIM, Cha, Wee ,  YI-SHENG, Anthony, Sun ,  HETZEL, Wolfgang ,  THOMAS, Jochen

Inventor： LENG, Chen Fung ,  KWANG, Brandon, Kim, Seong ,  LIM, Cha, Wee ,  YI-SHENG, Anthony, Sun ,  HETZEL, Wolfgang ,  THOMAS, Jochen

IPC: H01L21/00

CPC classification number: H01L24/32 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running lengthwise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

Abstract translation: 公开了一种BGA封装，其包括具有基础衬底的基础IC结构，具有穿过纵向延伸的开口。 第一半导体芯片面朝下地安装在基础衬底上，使得其接合焊盘可通过开口接近。 该封装还包括次级IC结构，该次级IC结构包括具有穿过其中的开口的次级衬底以及第二半导体芯片。 第二芯片面朝下地安装在辅助基板上，使得其接合垫可通过辅助基板中的开口接近。 密封剂填充副衬底中的开口并且在副衬底的下侧上形成基本平坦的表面。 基本平坦的表面通过粘合剂安装到基础IC结构的第一芯片上。 导线将次级IC结构的导电部分连接到基础IC结构的导电部分。

公开(公告)号：WO2004070790A2

公开(公告)日：2004-08-19

申请号：PCT/US2004/002985

申请日：2004-02-03

Applicant: UNITED TEST AND ASSEMBLY CENTER LTD. ,  XILINX INC. ,  GOH, Kim Yong ,  KAPOOR, Rahul ,  SUN, Anthony Yi-Sheng ,  CHONG, Desmond Yok Rue ,  HOANG, Lan H.

Inventor： GOH, Kim Yong ,  KAPOOR, Rahul ,  SUN, Anthony Yi-Sheng ,  CHONG, Desmond Yok Rue ,  HOANG, Lan H.

IPC: H01L

CPC classification number: H01L23/4334 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/1659 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/0401 ,  H01L2924/00

Abstract: A thermally enhanced ball grid array package is disclosed. The package includes a base layer element and a flip chip die mounted on the base layer element. The die has a first surface electrically coupled to the base layer element, a second surface opposite to the first surface, and lateral sides. A molding compound encapsulates the base layer element and the lateral sides of the die. A surface is formed of the second surface of the die and an upper surface of the molding compound. A material is disposed on the surface, and a heat spreader is mounted on the material.

Abstract translation: 公开了一种热增强球栅阵列封装。 封装包括安装在基底层元件上的基底元件和倒装芯片裸片。 模具具有电耦合到基层元件的第一表面，与第一表面相对的第二表面和横向侧面。 模制化合物封装基底层元件和模具的侧面。 表面由模具的第二表面和模塑料的上表面形成。 材料设置在表面上，散热器安装在材料上。