-
1.INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY 审中-公开
Title translation: 使用顶尖后置技术和底部结构技术的集成电路芯片公开(公告)号:WO2010114687A1
公开(公告)日:2010-10-07
申请号:PCT/US2010/027056
申请日:2010-03-11
Applicant: MEGICA CORPORATION , LIN, Mou-Shiung , LEE, Jin-Yuan , LO, Hsin-Jung , YANG, Ping-Jung , LIU, Te-Sheng
Inventor: LIN, Mou-Shiung , LEE, Jin-Yuan , LO, Hsin-Jung , YANG, Ping-Jung , LIU, Te-Sheng
CPC classification number: G06F1/16 , G11C5/147 , H01L21/563 , H01L23/3128 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L23/60 , H01L23/66 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/50 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2223/6611 , H01L2223/6666 , H01L2224/02166 , H01L2224/02311 , H01L2224/02313 , H01L2224/02321 , H01L2224/0233 , H01L2224/02331 , H01L2224/0235 , H01L2224/0237 , H01L2224/02371 , H01L2224/02375 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/03612 , H01L2224/03614 , H01L2224/03912 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05024 , H01L2224/05027 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05176 , H01L2224/05181 , H01L2224/05187 , H01L2224/05541 , H01L2224/05548 , H01L2224/05554 , H01L2224/0556 , H01L2224/05567 , H01L2224/05572 , H01L2224/056 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/05673 , H01L2224/05676 , H01L2224/11 , H01L2224/11009 , H01L2224/1132 , H01L2224/11334 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/119 , H01L2224/1191 , H01L2224/13 , H01L2224/13006 , H01L2224/1302 , H01L2224/13022 , H01L2224/13024 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/13099 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2224/13294 , H01L2224/133 , H01L2224/13311 , H01L2224/13609 , H01L2224/1403 , H01L2224/1411 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/16265 , H01L2224/17181 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/29339 , H01L2224/32105 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48111 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48664 , H01L2224/48669 , H01L2224/48764 , H01L2224/48769 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/48864 , H01L2224/4911 , H01L2224/49175 , H01L2224/4918 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73257 , H01L2224/73265 , H01L2224/81191 , H01L2224/81411 , H01L2224/81444 , H01L2224/81801 , H01L2224/81815 , H01L2224/8185 , H01L2224/81895 , H01L2224/81903 , H01L2224/83101 , H01L2224/83104 , H01L2224/83851 , H01L2224/92 , H01L2224/9202 , H01L2224/92125 , H01L2224/92127 , H01L2224/92147 , H01L2224/92225 , H01L2224/92247 , H01L2224/94 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/1029 , H01L2225/1058 , H01L2225/107 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01059 , H01L2924/01068 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/1421 , H01L2924/1433 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/19105 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2224/48869 , H01L2224/48744 , H01L2924/00012 , H01L2224/03 , H01L2224/0361 , H01L2924/0665 , H01L2224/81 , H01L2224/83 , H01L24/78 , H01L2224/85 , H01L21/56 , H01L21/78 , H01L2924/0635 , H01L2924/07025 , H01L21/304 , H01L21/76898 , H01L2224/0231
Abstract: Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described.
Abstract translation: 公开了集成电路芯片和芯片封装,其包括在集成电路芯片的顶部处的过钝化方案,以及使用顶部后钝化技术和底部结构技术的集成电路芯片的底部的底部方案。 集成电路芯片可以通过过钝化方案或者通过钝化方案连接到外部电路或结构,例如球栅阵列(BGA)衬底,印刷电路板,半导体芯片,金属衬底,玻璃衬底或陶瓷衬底 底部方案。 描述了相关的制造技术。
-
2.
公开(公告)号:WO2004088727A2
公开(公告)日:2004-10-14
申请号:PCT/IB2004/001734
申请日:2004-04-02
Applicant: UNITED TEST AND ASSEMBLY CENTER LTD. , INFINEON, TECHNOLOGIES , LENG, Chen Fung , KWANG, Brandon, Kim, Seong , LIM, Cha, Wee , YI-SHENG, Anthony, Sun , HETZEL, Wolfgang , THOMAS, Jochen
Inventor: LENG, Chen Fung , KWANG, Brandon, Kim, Seong , LIM, Cha, Wee , YI-SHENG, Anthony, Sun , HETZEL, Wolfgang , THOMAS, Jochen
IPC: H01L21/00
CPC classification number: H01L24/32 , H01L23/13 , H01L23/3121 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/105 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/92147 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01058 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running lengthwise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.
Abstract translation: 公开了一种BGA封装,其包括具有基础衬底的基础IC结构,具有穿过纵向延伸的开口。 第一半导体芯片面朝下地安装在基础衬底上,使得其接合焊盘可通过开口接近。 该封装还包括次级IC结构,该次级IC结构包括具有穿过其中的开口的次级衬底以及第二半导体芯片。 第二芯片面朝下地安装在辅助基板上,使得其接合垫可通过辅助基板中的开口接近。 密封剂填充副衬底中的开口并且在副衬底的下侧上形成基本平坦的表面。 基本平坦的表面通过粘合剂安装到基础IC结构的第一芯片上。 导线将次级IC结构的导电部分连接到基础IC结构的导电部分。 p>
-
3.MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF 审中-公开
Title translation: 具有堆叠微电子单元的微电子封装及其制造方法公开(公告)号:WO2013059297A1
公开(公告)日:2013-04-25
申请号:PCT/US2012/060585
申请日:2012-10-17
Applicant: INVENSAS CORPORATION
Inventor: CASKEY, Terrence , MOHAMMED, Ilyas
CPC classification number: H01L25/18 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76877 , H01L23/13 , H01L23/3107 , H01L23/3114 , H01L23/3185 , H01L23/49816 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05124 , H01L2224/05147 , H01L2224/05548 , H01L2224/05554 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/06155 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/1329 , H01L2224/133 , H01L2224/14131 , H01L2224/27334 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48108 , H01L2224/48145 , H01L2224/4824 , H01L2224/73207 , H01L2224/73215 , H01L2224/73217 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/83005 , H01L2224/83192 , H01L2224/852 , H01L2224/92144 , H01L2224/92147 , H01L2225/06506 , H01L2225/0651 , H01L2225/06548 , H01L2225/06562 , H01L2225/06596 , H01L2225/1035 , H01L2225/1052 , H01L2225/1076 , H01L2225/1082 , H01L2924/00014 , H01L2924/0665 , H01L2924/12042 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/18162 , H01L2924/186 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/05552
Abstract: A microelectronic package (10) may include a first microelectronic unit (12) including a semiconductor chip (16A) having first chip contacts (28), an encapsulant (30) contacting an edge of the semiconductor chip, and first unit contacts (42) exposed at a surface of the encapsulant (30) and electrically connected with the first chip contacts (28). The package (10) may include a second microelectronic unit (14) including a semiconductor chip (16C) having second chip contacts (28C) at a surface thereof, and an encapsulant (54) contacting an edge of the chip of the second unit (14) and having a surface extending away from the edge. The surfaces of the chip (16C) and the encapsulant (54) of the second unit (14) define a face of the second unit. Package terminals (76) at the face may be electrically connected with the first unit contacts (42) through bond wires (100) electrically connected with the first unit contacts (42), and the second chip contacts (28C) through metallized vias (72) and traces (74) formed in contact with the second chip contacts (28C).
Abstract translation: 微电子封装(10)可以包括第一微电子单元(12),其包括具有第一芯片触点(28)的半导体芯片(16A),与半导体芯片的边缘接触的密封剂(30)和第一单元触点(42) 暴露在密封剂(30)的表面处并与第一芯片触头(28)电连接。 封装(10)可以包括第二微电子单元(14),其包括在其表面具有第二芯片触点(28C)的半导体芯片(16C)和与第二单元的芯片的边缘接触的密封剂(54) 并且具有远离边缘延伸的表面。 芯片(16C)和第二单元(14)的密封剂(54)的表面限定第二单元的面。 面上的封装端子(76)可以通过与第一单元触点(42)电连接的接合线(100)和第二芯片触点(28C)穿过金属化通孔(72)与第一单元触点(42)电连接 )和与第二芯片触点(28C)接触形成的迹线(74)。
-
4.SEMICONDUCTOR CHIP STACK PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开
Title translation: 半导体芯片堆栈及其制造方法公开(公告)号:WO2012086871A1
公开(公告)日:2012-06-28
申请号:PCT/KR2011/001166
申请日:2011-02-22
Applicant: KOREA INSTITUTE OF MACHINERY & MATERIALS , LEE, Jae-Hak , LEE, Chang-Woo , SONG, Joon-Yub , HA, Tae-Ho
Inventor: LEE, Jae-Hak , LEE, Chang-Woo , SONG, Joon-Yub , HA, Tae-Ho
CPC classification number: H01L23/488 , H01L21/50 , H01L24/26 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/04042 , H01L2224/26145 , H01L2224/27013 , H01L2224/29139 , H01L2224/2919 , H01L2224/29191 , H01L2224/32145 , H01L2224/48091 , H01L2224/73215 , H01L2224/73265 , H01L2224/82143 , H01L2224/83002 , H01L2224/83051 , H01L2224/83143 , H01L2224/83192 , H01L2224/9205 , H01L2224/92147 , H01L2225/0651 , H01L2225/06562 , H01L2225/06593 , H01L2924/00014 , H01L2924/10253 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity.
Abstract translation: 半导体芯片堆叠封装及其制造方法技术领域本发明涉及一种半导体芯片堆叠封装及其制造方法,更具体地,涉及一种半导体芯片堆叠封装及其制造方法,其中可以在没有精确的装置或操作的情况下快速地布置和粘合多个芯片 以提高生产率。
-
5.MULTI-CHIP BALL GRID ARRAY PACKAGE AND METHOD OF MANUFACTURE 审中-公开
Title translation: 多芯球网阵列包装及其制造方法公开(公告)号:WO2004088727B1
公开(公告)日:2005-03-10
申请号:PCT/IB2004001734
申请日:2004-04-02
Applicant: UNITED TEST & ASSEMBLY CT LTD , INFINEON TECHNOLOGIES , CHEN FUNG LENG , KIM SEONG KWANG BRANDON , CHA WEE LIM , SUN YI-SHENG ANTHONY , HETZEL WOLFGANG , THOMAS JOCHEN
Inventor: CHEN FUNG LENG , KIM SEONG KWANG BRANDON , CHA WEE LIM , SUN YI-SHENG ANTHONY , HETZEL WOLFGANG , THOMAS JOCHEN
IPC: H01L23/13 , H01L23/31 , H01L23/498 , H01L25/10
CPC classification number: H01L24/32 , H01L23/13 , H01L23/3121 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/105 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/92147 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01058 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: A BGA package (500) is disclosed including a base IC structure (300) having a base substrate (302), with an opening (301c) running lengthwise therethrough. A first semiconductor chip (315) is mounted face-down on the base substrate (301) so that the bond pads (317) thereof are accessible through the opening (301c). The package (500) also includes a secondary IC structure (400) including a secondary substrate (401), having an opening (401c) running there through, and a second semiconductor chip (415). The second chip (415) is mounted face-down on the secondary substrate (401) so that the bond pads (417) thereof are accessible through the opening (401c) in the secondary substrate (401). An encapsulant (425) fills the opening (401c) in the secondary substrate (401) and forms a substantially planar surface (425a) over the underside of the secondary substrate (401). The substantially planar surface (425a) is mounted to the first chip (315) of the base IC structure (300) through an adhesive (504). Wires (521) connect a conductive portion (406) of the secondary IC structure (400) to a conductive portion (303) of the base IC structure (300).
Abstract translation: 公开了一种BGA封装(500),其包括具有基底基板(302)的基底IC结构(300),其中纵向延伸穿过其中的开口(301c)。 第一半导体芯片(315)正面朝下地安装在基底(301)上,使得其接合焊盘(317)可通过开口(301c)接近。 封装(500)还包括具有第二衬底(401)的辅助IC结构(400),其具有在其上延伸的开口(401c)和第二半导体芯片(415)。 第二芯片(415)正面朝下安装在辅助基板(401)上,使得其接合焊盘(417)可通过次级基板(401)中的开口(401c)接近。 密封剂(425)填充次级衬底(401)中的开口(401c)并在次级衬底(401)的下侧上形成基本平坦的表面(425a)。 基本平坦的表面(425a)通过粘合剂(504)安装到基座IC结构(300)的第一芯片(315)上。 电线(521)将二次IC结构(400)的导电部(406)与基极IC结构(300)的导电部(303)连接。
-
公开(公告)号:WO2012046695A1
公开(公告)日:2012-04-12
申请号:PCT/JP2011/072786
申请日:2011-10-03
Applicant: 日立化成工業株式会社 , 杉浦 良史 , 藤井 真二郎 , 森 修一
IPC: H01L21/52 , C09J5/06 , C09J11/00 , C09J201/00
CPC classification number: H01L23/3128 , C09J5/06 , C09J2203/326 , C09J2205/31 , H01L24/27 , H01L24/29 , H01L24/48 , H01L24/743 , H01L24/83 , H01L24/85 , H01L2224/2732 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29386 , H01L2224/29387 , H01L2224/32012 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/83192 , H01L2224/83805 , H01L2224/83856 , H01L2224/85 , H01L2224/92147 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/12041 , H01L2924/12044 , H01L2924/15311 , H01L2924/15747 , H01L2924/15788 , H01L2924/1815 , H01L2924/00 , H01L2924/01014 , H01L2924/00012 , H01L2924/3512 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: 本発明の半導体装置の製造方法は、半導体チップを搭載するための半導体支持部材10上に、光硬化性成分及び熱硬化性成分を含み溶剤の含有量が5質量%以下であるダイボンディング用樹脂ペーストを印刷法により塗布して樹脂ペーストの塗膜30を設ける第1工程と、塗膜30への光照射により光硬化性成分を光硬化する第2工程と、半導体支持部材10と半導体チップ50とを、光照射された塗膜32を挟んで圧着して接合する第3工程とを備えることを特徴とする。また、本発明のダイボンディング用樹脂ペーストは、25℃における粘度が100Pa・s以下である光重合性化合物、熱硬化性化合物、及び熱可塑性エラストマーを含有し、溶剤の含有量が5質量%以下であることを特徴とする。
Abstract translation: 该半导体装置的制造方法的特征在于,提供:通过涂布粘合剂用树脂膏(5质量%以下)含有光固化性成分的溶剂含量为5质量%以下的第1工序, 可热固化组分施加到用于安装半导体芯片的半导体支撑构件(10); 通过用光照射涂层(30)来光固化组分的第二步骤; 以及第三步骤,通过压力夹持,连接半导体支撑构件(10)和半导体芯片(50)之间的光照射涂层(32)。 此外,该粘合用树脂糊的特征在于,含有25℃下的粘度为100Pa·s的可光聚合化合物,热固性化合物和热塑性弹性体,溶剂含量为5质量%以下 。
-
7.ダイボンディング用樹脂ペースト、それを用いた半導体装置の製造方法、及び半導体装置 审中-公开
Title translation: 用于DIE结合的树脂粘合剂,使用树脂粘合剂和半导体器件生产半导体器件的工艺公开(公告)号:WO2010110069A1
公开(公告)日:2010-09-30
申请号:PCT/JP2010/054027
申请日:2010-03-10
IPC: H01L21/52 , C08G59/40 , C09J163/00
CPC classification number: H01L23/295 , C08G59/186 , C09J163/00 , H01L23/3107 , H01L24/27 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/743 , H01L24/83 , H01L2224/0401 , H01L2224/05624 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/29298 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/48247 , H01L2224/484 , H01L2224/48624 , H01L2224/48639 , H01L2224/73215 , H01L2224/73265 , H01L2224/83805 , H01L2224/83855 , H01L2224/83856 , H01L2224/85439 , H01L2224/92147 , H01L2924/00011 , H01L2924/00013 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/09701 , H01L2924/10253 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/15788 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2924/01014 , H01L2924/01079 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/83205
Abstract: Bステージ化において、広い温度範囲でチップとの接着強度に優れると共に、チップとの間のボイドも低減でき、且つ、半田リフロー工程においても熱時ダイシェア強度に優れるダイボンディング用樹脂ペーストを提供する。 カルボキシル基を有するブタジエンのポリマー(a1)とエポキシ基を有する化合物(a2)を反応させて得られるポリマー(A)、熱硬化性樹脂(B)及びフィラー(C)を含むダイボンディング用樹脂ペーストである。
Abstract translation: 公开了一种用于芯片接合的树脂浆料,其在B阶段中输送树脂浆料的过程中在宽温度范围内具有优异的粘合强度,并且在回流焊接过程中在高温下也具有优异的模头剪切强度。 用于芯片接合的树脂浆料包括:(A)通过使(a1)具有羧基的丁二烯的聚合物与(a2)具有环氧基的化合物反应制备的聚合物; (B)热固性树脂; 和(C)填料。
-
公开(公告)号:WO2010098500A1
公开(公告)日:2010-09-02
申请号:PCT/JP2010/053487
申请日:2010-02-25
CPC classification number: H01L23/49503 , H01L24/03 , H01L24/05 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/85 , H01L24/97 , H01L2224/02166 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05554 , H01L2224/05558 , H01L2224/05624 , H01L2224/29339 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48479 , H01L2224/48499 , H01L2224/48624 , H01L2224/48799 , H01L2224/49171 , H01L2224/73265 , H01L2224/7825 , H01L2224/78301 , H01L2224/78703 , H01L2224/85045 , H01L2224/85051 , H01L2224/85075 , H01L2224/851 , H01L2224/85181 , H01L2224/85186 , H01L2224/85203 , H01L2224/85205 , H01L2224/85986 , H01L2224/92 , H01L2224/92147 , H01L2224/92247 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/00015 , H01L2924/01005 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01203 , H01L2924/01204 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/10162 , H01L2924/12041 , H01L2924/181 , H01L2924/20753 , H01L2924/20754 , H01L2924/3025 , H01L2224/85 , H01L2224/48472 , H01L2924/00 , H01L2924/00012 , H01L2224/48227 , H01L2924/3512 , H01L2224/48824 , H01L2924/01006 , H01L2224/4554
Abstract: アイランド7上に半導体素子10が固着され、半導体素子10の固着領域の周囲のアイランド7には、複数の貫通孔8が形成される。そして、半導体素子10の電極パッドとリード4とは銅線11により電気的に接続される。この構造により、銅線11を用いることで金線の場合と比較して材料コストが低減される。また、樹脂パッケージ2の一部が貫通孔8内を埋設することで、アイランド7が樹脂パッケージ2内に支持され易い構造となる。
Abstract translation: 半导体元件(10)被固定到岛(7)上,并且在岛(7)的部分中形成有多个通孔(8),其围绕半导体元件(10)所在的区域 担保。 此外,半导体元件(10)的电极焊盘和引线(4)通过铜线(11)电连接。 在这种结构中,通过使用铜线(11)与金线相比,材料的成本降低。 此外,树脂封装(2)的一部分嵌入在通孔(8)中,使得岛(7)能够容易地支撑在树脂封装(2)内。
-
9.MULTI-CHIP BALL GRID ARRAY PACKAGE AND METHOD OF MANUFACTURE 审中-公开
Title translation: 多芯球网阵列包装及其制造方法公开(公告)号:WO2004088727A3
公开(公告)日:2004-11-11
申请号:PCT/IB2004001734
申请日:2004-04-02
Applicant: UNITED TEST & ASSEMBLY CT LTD , INFINEON TECHNOLOGIES , CHEN FUNG LENG , KIM SEONG KWANG BRANDON , CHA WEE LIM , SUN YI-SHENG ANTHONY , HETZEL WOLFGANG , THOMAS JOCHEN
Inventor: CHEN FUNG LENG , KIM SEONG KWANG BRANDON , CHA WEE LIM , SUN YI-SHENG ANTHONY , HETZEL WOLFGANG , THOMAS JOCHEN
IPC: H01L23/13 , H01L23/31 , H01L23/498 , H01L25/10
CPC classification number: H01L24/32 , H01L23/13 , H01L23/3121 , H01L23/49816 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/105 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/92147 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01058 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running lengthwise therethrough. A first semiconductor chip is mounted face-down on the base substrate so that the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.
Abstract translation: 公开了一种BGA封装,其包括具有基底基板的基底IC结构,其开口纵向穿过其中。 第一半导体芯片正面朝下安装在基底基板上,使得它们的接合焊盘可通过开口接近。 该封装还包括一个次级IC结构,该二级IC结构包括一个具有在其上延伸的开口的次级衬底和一个第二半导体芯片。 第二芯片正面朝下安装在二次基板上,使得其接合焊盘可通过次级基板中的开口接近。 密封剂填充次级基底中的开口并且在次级基底的下侧上形成基本平坦的表面。 基本平坦的表面通过粘合剂安装到基底IC结构的第一芯片。 导线将次级IC结构的导电部分连接到基极IC结构的导电部分。
-
10.STRUCTURES AND METHODS FOR SHIELDING MAGNETICALLY SENSITIVE COMPONENTS 审中-公开
Title translation: 用于屏蔽磁敏感组件的结构和方法公开(公告)号:WO2015175872A1
公开(公告)日:2015-11-19
申请号:PCT/US2015/030959
申请日:2015-05-15
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor: LIN, Wenchin , JANESKY, Jason
IPC: G11C11/15 , H01L23/14 , H01L23/552
CPC classification number: H01L43/02 , G11C5/005 , G11C11/16 , H01L23/13 , H01L23/14 , H01L23/49816 , H01L23/49838 , H01L23/552 , H01L24/06 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L27/222 , H01L43/12 , H01L2224/04042 , H01L2224/06136 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/45015 , H01L2224/4824 , H01L2224/49175 , H01L2224/73215 , H01L2224/83191 , H01L2224/83192 , H01L2224/85203 , H01L2224/85205 , H01L2224/92147 , H01L2924/00014 , H01L2924/1441 , H01L2924/15311 , H01L2924/00 , H01L2224/45099 , H01L2924/207
Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.
Abstract translation: 公开了用于屏蔽磁敏元件的结构和方法。 一种结构包括衬底,沉积在衬底上的底部屏蔽,具有第一表面和与第一表面相对的第二表面的磁阻半导体器件,沉积在底部屏蔽上的磁阻半导体器件的第一表面,沉积在 磁阻半导体器件的第二表面,顶部屏蔽件具有用于访问磁阻半导体器件的窗口,以及将磁阻半导体器件连接到多个导电元件的多个互连。
-
-
-
-
-
-
-
-
-