公开(公告)号：WO1998025298A1

公开(公告)日：1998-06-11

申请号：PCT/JP1997004438

申请日：1997-12-04

Applicant: SEIKO EPSON CORPORATION ,  HASHIMOTO, Nobuaki

Inventor： SEIKO EPSON CORPORATION

IPC: H01L21/3205

CPC classification number: H01L24/11 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device whose package size is nearly the same as the size of a chip, and which can effectively absorb thermal stress in addition to a stress absorbing layer. A semiconductor device (150) has semiconductor chip having an electrode (158), a resin layer (152) formed as a stress reducing layer on the semiconductor chip, an interconnect (154) which is formed on the entire surface including the electrode (158) and the resin layer (152), and a solder ball (157) which is formed on a part of the interconnect (154) which is formed on the resin layer (152). The resin layer (152) is so formed as to have a recess (152a) on its surface and the interconnect (154) is so formed as to also cover the entire surface including the recess (152a).

Abstract translation: 一种半导体器件，其封装尺寸与芯片的尺寸几乎相同，并且除了应力吸收层之外还可以有效地吸收热应力。 半导体器件（150）具有半导体芯片，其具有电极（158），在半导体芯片上形成为应力降低层的树脂层（152），形成在包括电极（158）的整个表面上的互连 ）和树脂层（152），以及形成在形成在树脂层（152）上的互连件（154）的一部分上的焊球（157）。 树脂层（152）形成为在其表面上具有凹部（152a），并且互连（154）形成为也覆盖包括凹部（152a）的整个表面。

公开(公告)号：WO1998018164A1

公开(公告)日：1998-04-30

申请号：PCT/JP1997003459

申请日：1997-09-29

Applicant: SEIKO EPSON CORPORATION ,  HASHIMOTO, Nobuaki

Inventor： SEIKO EPSON CORPORATION

IPC: H01L23/12

CPC classification number: H01L21/563 ,  H01L23/3107 ,  H01L23/3114 ,  H01L2224/73203 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: A semiconductor device which can be guaranteed for quality and can be handled easily and in which the electrodes of a semiconductor chip can be joined collectively to a flexible substrate, a method for manufacturing the semiconductor device, a circuit board, and a flexible substrate. A gap holding member (16) is provided on the surface of the flexible substrate (12) on which a joining section (24) which joins the substrate (12) to the electrodes (14) of the semiconductor chip (10) is positioned and the member (16) is interposed between the chip (10) and a substrate (12). Then, the joining section (24) on the substrate (12) is joined to the electrodes (14) of the chip (10) and a stress absorbing layer (26) is formed by injecting a moulding material into the space between the substrate (2) and the chip (10).

Abstract translation: 可以保证质量可以容易地处理的半导体器件，其中可以将半导体芯片的电极集体地连接到柔性衬底，半导体器件的制造方法，电路板和柔性衬底。 在柔性基板（12）的表面上设置间隙保持部件（16），在该表面上，与基板（12）连接到半导体芯片（10）的电极（14）的接合部分（24）位于其上， 构件（16）插入在芯片（10）和基板（12）之间。 然后，将基板（12）上的接合部（24）与芯片（10）的电极（14）接合，通过将成型材料注入到基板（10）的空间内，形成应力吸收层（26） 2）和芯片（10）。

公开(公告)号：WO1998018162A1

公开(公告)日：1998-04-30

申请号：PCT/JP1997003599

申请日：1997-10-08

Applicant: SEIKO EPSON CORPORATION ,  HASHIMOTO, Nobuaki

Inventor： SEIKO EPSON CORPORATION

IPC: H01L21/60

CPC classification number: H01L24/86 ,  H01L23/49572 ,  H01L23/4985 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/241 ,  H01L2924/00

Abstract: A semiconductor device which is manufactured by the process using a film carrier tape and has a package size which is nearly equal to the size of a chip and into which a sealing resin can be injected in an excellent state, and a method for manufacturing the device. The film carrier tape (32) has a plurality of connecting leads (24), connecting sections formed by connecting some of the leads (24), holes (29 and 31) formed by punching intersections, and rectangular holes (11-15), and the sealing resin is injected into the device through the rectangular holes (11 and 15). The rectangular holes (12 and 14) work to stop the spreading of the resin, and the holes (29 and 31) work as vent holes for exhausting the air from the resin.

Abstract translation: 一种半导体器件，其通过使用薄膜载带的方法制造，并且具有几乎等于芯片的尺寸的封装尺寸，并且密封树脂可以以优异的状态注入到该半导体器件中，以及该器件的制造方法 。 薄膜载体带（32）具有多个连接引线（24），通过连接一些引线（24），通过冲孔相交形成的孔（29和31）以及矩形孔（11-15）形成的连接部分， 并且密封树脂通过矩形孔（11和15）注入到装置中。 矩形孔（12和14）用于停止树脂的铺展，并且孔（29和31）作为用于从树脂排出空气的通气孔。

公开(公告)号：WO1998018161A1

公开(公告)日：1998-04-30

申请号：PCT/JP1997003458

申请日：1997-09-29

Applicant: SEIKO EPSON CORPORATION ,  HASHIMOTO, Nobuaki

Inventor： SEIKO EPSON CORPORATION

IPC: H01L21/60

CPC classification number: H01L24/86 ,  H01L23/49572 ,  H01L23/4985 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/241 ,  H01L2924/00

Abstract: A semiconductor device which is manufactured by using a film carrier tape and has a package size nearly equal to the chip size, and in which the portions of the semiconductor chip connected with the electrodes are not exposed to the outside, and a method of manufacturing the semiconductor device. The film carrier tape comprises connection leads (24) formed in the region to be filled with a molding material (36) and adapted to be joined to the electrodes (42) and pads (22) of a semiconductor chip (40), plated leads (26) to be connected with the connection leads (24), and plated electrodes (28) to be connected with the plated leads (26). These components are electroplated, with all the components electrically connected. Connection portions (29) extending into the region to be filled with the molding material are removed by punching to join the connection leads (24) and the electrodes (42), and the molding material (36) is fed. Even the end faces of the connection leads (24) exposed from holes (32) are covered with the molding material (36), so that they are not exposed to the outside.

Abstract translation: 一种半导体器件，其通过使用胶片载带制造，并且具有几乎等于芯片尺寸的封装尺寸，并且其中与电极连接的半导体芯片的部分不暴露于外部，并且其中制造 半导体器件。 薄膜载体带包括形成在待填充模塑材料的区域中并连接到半导体芯片（40）的电极（42）和焊盘（22）的区域中的连接引线（24），电镀引线 （26）与连接引线（24）连接，以及与电镀引线（26）连接的电镀电极（28）。 这些组件是电镀的，所有组件都电连接。 通过冲压去除延伸到要被模制材料填充的区域的连接部分（29），以连接连接引线（24）和电极（42），并且馈送模制材料（36）。 甚至从孔（32）露出的连接引线（24）的端面也被模制材料（36）覆盖，使得它们不暴露于外部。

公开(公告)号：WO1998003990A1

公开(公告)日：1998-01-29

申请号：PCT/JP1997002304

申请日：1997-07-03

Applicant: SEIKO EPSON CORPORATION ,  HASHIMOTO, Nobuaki

Inventor： SEIKO EPSON CORPORATION

IPC: H01L21/60

CPC classification number: H01L24/81 ,  H01L31/02002 ,  H01L31/0203 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A novel technique of easily and inexpensively mounting an optical converter and semiconductor devices on a printed wiring board at a high density. Before an encapsulated body is mounted on a printed wiring board (400), an opening (340) is made in the board, and conductive bonding portions (360b) are provided on the base member (100). The body is bonded face-down. At least part of the body is fitted in the opening (340), and therefore the height of the body from the surface of the board is small, permitting the face-down bonding.

Abstract translation: 一种以高密度将光转换器和半导体器件容易且廉价地安装在印刷线路板上的新颖技术。 在将封装体安装在印刷电路板（400）上之前，在基板上形成开口（340），并且在基体（100）上设置导电接合部（360b）。 身体正面朝下。 身体的至少一部分安装在开口（340）中，因此，主体从板表面的高度很小，从而允许面朝下的粘合。

公开(公告)号：WO1998025297A1

公开(公告)日：1998-06-11

申请号：PCT/JP1997004437

申请日：1997-12-04

Applicant: SEIKO EPSON CORPORATION ,  HASHIMOTO, Nobuaki

Inventor： SEIKO EPSON CORPORATION

IPC: H01L21/3205

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/14131 ,  H01L2224/16 ,  H01L2224/73104 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor device whose package size is nearly the same as the size of a chip, which has a stress absorbing layer, which does not require a flexible substrate, and which can be manufactured in a large number at the same time. A method for manufacturing a semiconductor device includes a process wherein electrodes (12) are formed on a wafer (10), a process wherein a resin layer (14) is formed as a stress reducing layer on the wafer (10) except for the parts where the electrodes (12) are formed, a process wherein a chrome layer (16) is formed as an interconnect on the whole surface of the wafer (10) including the electrodes (12) and the resin layer (14), a process wherein solder balls are formed as external electrodes on parts of the chrome layer (16) which are formed on the resin layer (14), and a process wherein the wafer (10) is diced to semiconductor chips. In the processes for forming the chrome layer (16) and for forming the solder balls, a metal thin film deposition technology used in the wafer process of semiconductor manufacturing is employed.

Abstract translation: 其封装尺寸与具有不需要柔性基板的应力吸收层的芯片的尺寸几乎相同的半导体器件，并且可以同时大量地制造。 一种制造半导体器件的方法包括其中在晶片（10）上形成电极（12）的工艺，其中在晶片（10）之外形成树脂层（14）作为应力降低层的工艺，除了部件 在形成电极（12）的方法中，在包括电极（12）和树脂层（14）的晶片（10）的整个表面上形成铬层（16）作为互连的工艺，其中 在形成在树脂层（14）上的铬层（16）的部分上形成焊球作为外部电极，以及将晶片（10）切割成半导体芯片的工序。 在用于形成铬层（16）和形成焊球的工艺中，采用在半导体制造的晶片工艺中使用的金属薄膜沉积技术。

公开(公告)号：WO1998018163A1

公开(公告)日：1998-04-30

申请号：PCT/JP1997003707

申请日：1997-10-15

Applicant: SEIKO EPSON CORPORATION ,  HASHIMOTO, Nobuaki

Inventor： SEIKO EPSON CORPORATION

IPC: H01L21/60

CPC classification number: H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A film carrier tape which makes it possible to reduce bending of leads in a manufacturing process, to produce a chip-size package with high reliability and to improve a production yield. The distal end portions of leads (54a, 54b) of a TAB are left as free ends from the pattern formation step without being connected to a frame (59) and are not at all processed till the final bonding step. On the other hand, a plurality of connecting portions (57a to 57j) are disposed in a packaging area of a semiconductor chip, and a large number of leads are connected to the connecting portions at the inner side of the packaging surface of one IC chip and are electrically connected to the frame through the connecting portions.

Abstract translation: 一种薄膜载体带，其可以在制造过程中减少引线的弯曲，从而制造具有高可靠性的芯片尺寸封装并提高产量。 TAB的引线（54a，54b）的前端部从图案形成步骤保持为自由端而不连接到框架（59），并且在完成加工直到最终粘合步骤之前。 另一方面，多个连接部分（57a至57j）设置在半导体芯片的封装区域中，并且多个引线连接到一个IC芯片的封装表面的内侧的连接部分 并通过连接部电连接到框架。

公开(公告)号：WO1999021181A1

公开(公告)日：1999-04-29

申请号：PCT/JP1997003750

申请日：1997-10-16

Applicant: SEIKO EPSON CORPORATION ,  YAMADA, Hideaki

Inventor： SEIKO EPSON CORPORATION

IPC: G11B07/09

CPC classification number: B23K26/04 ,  G11B7/0908 ,  G11B7/261

Abstract: A PD (81) is positioned at a predetermined position on an optical table, the rotation of a resist master (110) is stopped, a focusing laser (73) is driven, and a head (77) is positioned in a proper position by a head slider control circuit (101). The master (110) is turned, a focusing servo circuit (103) is started and, the PD (81) is moved horizontally by a focus fine adjustment circuit (99) by a minute distance corresponding to an estimated adequate focus position data. Since the difference between voltage signals from the two output terminals of the PD (81) is varied because of the surface vibration and minute movement caused by the rotation of the master (110), a differential amplifier (103a) moves a recording lens (77a) vertically by a distance of several microns so as to make an error signal zero. Numerical information on a digital display (93) at this time is compared with the focus position data. When both of them agree with each other, the focus position data is employed as an adequate focus position data and used for the initial setting of the adequate focus position. When they do not agree with each other, the numerical information is employed as the adequate focus position data and the focus position data is rewritten. By using the numerical adequate focus position data, the inital setting of the adequate focus position matching the type of the resist master can be carried out easily.

Abstract translation: PD（81）位于光学平台上的预定位置，停止抗蚀剂母体（110）的旋转，驱动聚焦激光（73），并且通过以下方式将头（77）定位在适当位置： 磁头滑块控制电路（101）。 主机（110）转动，聚焦伺服电路（103）启动，PD（81）由焦点微调电路（99）水平移动与估计的足够对焦位置数据相对应的微小距离。 由于由于主机（110）的旋转引起的表面振动和微小移动，PD（81）的两个输出端子的电压信号之间的差异是变化的，差分放大器（103a）使记录透镜（77a）移动 ）垂直延伸几微米的距离，以使误差信号为零。 此时将数字显示器（93）上的数值信息与焦点位置数据进行比较。 当它们都彼此一致时，聚焦位置数据被用作适当的聚焦位置数据，并用于初始设定足够的聚焦位置。 当它们不一致时，使用数字信息作为适当的焦点位置数据，并且重写焦点位置数据。 通过使用数值适当的聚焦位置数据，可以容易地进行与抗蚀剂母版类型匹配的适当聚焦位置的初始设置。

公开(公告)号：WO1998031104A1

公开(公告)日：1998-07-16

申请号：PCT/JP1997000019

申请日：1997-01-09

Applicant: SEIKO EPSON CORPORATION ,  SHIGEMORI, Mikio ,  KARASAWA, Hideo

Inventor： SEIKO EPSON CORPORATION

IPC: H03L07/08

CPC classification number: H01L24/06 ,  G06F1/08 ,  H01L23/49596 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01078 ,  H01L2924/12034 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/183 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2924/00012

Abstract: An inexpensive small-sized PLL (phase-locked loop) oscillator for use as the clock source of a computer, etc., which can output such a high frequency about 40 MHz that is difficult to obtain from a fundamental-based crystal oscillator. The oscillator operates as stably as the fundamental-based crystal oscillator does, is easy to set a frequency, can be produced in a short lead time, and can be easily handled like the conventional crystal oscillator. The PLL oscillator is housed in a package, which contains a piezoelectric vibrator, an oscillation circuit for driving the vibrator, and a PLL circuit which receives a reference signal from the oscillation circuit. The output frequency of the PLL oscillator is determined by the oscillation frequency of the oscillation circuit and the scaling factor of the programmable divider of the PLL circuit so that a prescribed output frequency can be obtained by selecting the corresponding scaling factor, which may be stored in a programmable read-only memory.

Abstract translation: 用作计算机时钟源的便宜的小型PLL（锁相环）振荡器等，其可以输出难以从基于基准的晶体振荡器获得的大约40MHz的高频。 振荡器的工作方式与基于基准的晶体振荡器一样稳定，易于设定频率，可以在短的提前期内产生，并且可以像常规的晶体振荡器那样容易地处理。 PLL振荡器容纳在包含压电振动器，用于驱动振动器的振荡电路和从振荡电路接收参考信号的PLL电路的封装中。 PLL振荡器的输出频率由振荡电路的振荡频率和PLL电路的可编程分频器的缩放因子决定，使得可以通过选择相应的缩放因子来获得规定的输出频率，该比例因子可以存储在 一个可编程只读存储器。

公开(公告)号：WO1998031095A1

公开(公告)日：1998-07-16

申请号：PCT/JP1997004623

申请日：1997-12-16

Applicant: SEIKO EPSON CORPORATION ,  IKEGAMI, Yasumitsu

Inventor： SEIKO EPSON CORPORATION

IPC: H03H09/19

CPC classification number: H03H9/0519 ,  H03H9/09 ,  Y10T29/42 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A piezoelectric vibrator so assembled that a space may be formed between a vibrating piece and a plug, with a conductive resin-made connection layer being formed for connecting, to the vibrating piece, a slab-like lead which has its top end opened in a U-shaped form. The top end of the lead can absorb shock due to its elasticity. Before forming the connection layer, a temporary fastening layer is formed between the top end of the lead and the vibrating piece using UV curing resin, or silver paste is applied to either the top end or the vibrating piece to increase the workability. By this method, piezoelectric vibrator units, which have a high resistance to shock and have a little change in frequency when being left in a high temperature environment and which are very reliable, can be mass-produced at low cost.

Abstract translation: 一种压电振动器，其被组装成可以在振动片和插塞之间形成空间，形成导电树脂制连接层，用于将振动片连接到其顶端开口的板状导线 U形形状。 铅的顶端由于其弹性而可以吸收冲击。 在形成连接层之前，使用UV固化树脂在引线的顶端和振动片之间形成临时的紧固层，或者将银膏施加到顶端或振动片上以提高加工性。 通过这种方法，可以以低成本批量生产具有高抗冲击性并且在高温环境中保持并且非常可靠的频率稍有变化的压电振动器单元。