公开(公告)号：EP3139277A1

公开(公告)日：2017-03-08

申请号：EP16188273.3

申请日：2002-04-23

申请人： Rambus Inc.

发明人： Ware, Frederick ,  Tsern, Ely K. ,  Perego, Richard E. ,  Hampel, Craig E.

IPC分类号： G06F13/16

摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

摘要翻译： 一种用于多样-位于存储器组件之间进行协调的存储器操作的方法和装置进行说明。 在与本发明的实施方式雅舞蹈，波浪流水线被实现为解决耦合到存储器元件的多个汇流。 存储器组件的多元性是被配置gemäß到坐标与地址总线传播延迟和数据总线传播延迟。 哪个复制合成信号的传播延迟与地址和/或控制信号相关联的定时信号用于协调存储器操作。

公开(公告)号：EP2894571B1

公开(公告)日：2017-03-08

申请号：EP15151769.5

申请日：2010-06-14

申请人： Rambus Inc.

发明人： Abbasfar, Aliazam

IPC分类号： G06F13/42

CPC分类号： G06F13/4265

公开(公告)号：EP3078191A1

公开(公告)日：2016-10-12

申请号：EP14868569.6

申请日：2014-12-03

申请人： Rambus Inc.

发明人： SMITH, Craig, M. ,  ARMSTRONG, Frank ,  ENDSLEY, Jay ,  VOGELSANG, Thomas ,  HARRIS, James, E. ,  LADD, John ,  GUIDASH, Michael

IPC分类号： H04N7/12

CPC分类号： H04N5/355 ,  H04N5/23245 ,  H04N5/2355 ,  H04N5/347 ,  H04N5/35536 ,  H04N5/361 ,  H04N5/37457 ,  H04N9/045

摘要： A pixel array within an integrated-circuit image sensor is exposed to light representative of a scene during a first frame interval and then oversampled a first number of times within the first frame interval to generate a corresponding first number of frames of image data from which a first output image may be constructed. One or more of the first number of frames of image data are evaluated to determine whether a range of luminances in the scene warrants adjustment of an oversampling factor from the first number to a second number, if so, the oversampling factor is adjusted such that the pixel array is oversampled the second number of times within a second frame interval to generate a corresponding second number of frames of image data from which a second output image may be constructed.

公开(公告)号：EP3069344A1

公开(公告)日：2016-09-21

申请号：EP14803317.8

申请日：2014-11-11

申请人： Rambus Inc.

发明人： WARE, Frederick A. ,  RAJAN, Suresh ,  BEST, Scott C.

IPC分类号： G11C5/04 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10

CPC分类号： G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

摘要翻译： 本文描述的实施例描述了在不同操作模式下使用存储器模块的技术，例如在标准多点模式或动态点对点（DPP）模式（此处也称为增强模式）中， 。 内存模块也可以以不同的配置插入存储系统的插座。

公开(公告)号：EP2539823B1

公开(公告)日：2016-04-13

申请号：EP10846793.7

申请日：2010-11-23

申请人： Rambus Inc.

发明人： SHAEFFER, Ian

IPC分类号： G06F13/16

CPC分类号： G06F13/1694 ,  G06F13/287 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4234

摘要： A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.

公开(公告)号：EP2965134A1

公开(公告)日：2016-01-13

申请号：EP14714454.7

申请日：2014-03-03

申请人： Rambus Inc.

发明人： GILL, Patrick, R. ,  STORK, David, G.

IPC分类号： G02B5/18 ,  G02B27/42 ,  G02B27/46 ,  H01L27/146 ,  H04N5/335 ,  G01S3/783

CPC分类号： G02B5/3083 ,  G02B5/1842 ,  G02B5/1871 ,  G02B27/4205 ,  G02B27/46 ,  H01L27/14625 ,  H01L27/14685 ,  H04N5/23232 ,  H04N5/335

摘要： Image-sensing devices include odd-symmetry gratings that cast interference patterns over a photodetector array. Grating features offer considerable insensitivity to the wavelength of incident light, and also to the manufactured distance between the grating and the photodetector array. Photographs and other image information can be extracted from interference patterns captured by the photodetector array. Images can be captured without a lens, and cameras can be made smaller than those that are reliant on lenses and ray-optical focusing.

公开(公告)号：EP2849075A8

公开(公告)日：2015-09-16

申请号：EP14196752.1

申请日：2002-04-23

申请人： Rambus Inc.

发明人： Ware, Frederick ,  Tsern, Ely K. ,  Perego, Richard E. ,  Hampel, Craig E.

IPC分类号： G06F13/16

CPC分类号： G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

公开(公告)号：EP1022641B2

公开(公告)日：2015-07-01

申请号：EP00100018.1

申请日：1991-04-16

申请人： Rambus Inc.

发明人： Farmwald, Michael ,  Horowitz, Mark

IPC分类号： G06F1/04 ,  G06F13/16 ,  G06F13/36 ,  G11C7/00 ,  G11C8/04

CPC分类号： G11C7/1066 ,  G06F11/006 ,  G06F11/1048 ,  G06F12/0215 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/1605 ,  G06F13/161 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/376 ,  G11C5/00 ,  G11C5/066 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/88 ,  G11C2207/105 ,  G11C2207/108 ,  Y02D10/13 ,  Y02D10/14

摘要： The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

公开(公告)号：EP2509075A3

公开(公告)日：2015-06-17

申请号：EP12171619.5

申请日：2007-12-13

申请人： Rambus Inc.

发明人： Best, Scott ,  Li, Ming

IPC分类号： G11C5/02

CPC分类号： G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/406 ,  G11C11/4096 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit (IC) package includes an interface die and a separate storage die. The interface die has a synchronous interface to receive memory access commands from an external memory controller, and has a plurality of clockless memory control interfaces to output row and column control signals that correspond to the memory access commands. The storage die has a plurality of independently accessible storage arrays and corresponding access-control interfaces to receive the row and column control signals from the clockless memory control interfaces, each of the access-control interfaces including data output circuitry to output read data corresponding to a given one of the memory access commands in a time-multiplexed transmission.

公开(公告)号：EP2751808A4

公开(公告)日：2015-04-08

申请号：EP12827743

申请日：2012-08-27

申请人： RAMBUS INC

发明人： VOGELSANG THOMAS

IPC分类号： G11C5/02 ,  G11C7/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

CPC分类号： G11C11/4091 ,  G11C5/025 ,  G11C7/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4097