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62 条记录 (耗时 0.018 秒)

    Multiple-value logic circuitry
    41.
    发明公开
    Multiple-value logic circuitry 失效
    Mehrwertige logische Schaltung。

    公开(公告)号：EP0220020A2

    公开(公告)日：1987-04-29

    申请号：EP86307758.2

    申请日：1986-10-08

    申请人： FUJITSU LIMITED

    发明人： Yokoyama, Naoki ,  Taguchi, Masao

    IPC分类号： G11C11/56 ,  H03K3/29 ,  H03K3/36

    CPC分类号： B82Y10/00 ,  F16L55/00 ,  G11C11/39 ,  G11C11/56 ,  G11C2211/5614 ,  H03K3/29 ,  H03K3/36

    摘要： Logic circuitry (1) includes a resonant-tunneling transistor ( 1) and a resistor (13) connected in series thereto.
    The resonant-tunneling transistor has a superlattice structure and may be a resonant-tunneling hot electron transistor or a resonant-tunneling bipolar transistor.
    The resonant-tunneling transistor is operable to flow a current, between a collector and an emitter, having one of at least three different current values of a first, a second or a third value in response to a base voltage (V IN ) in one of three different voltage values of a first, second or a third value. The third current value lies between the first and second current values, and the second voltage value lies between the first and third voltage values. The logic circuitry outputs one of at least three states having a high value, a low value, and a value approximately in between the high and low values in response to a signal applied to the logic circuitry the signal having an amplitude of one of the first to third voltage values.

    摘要翻译： 逻辑电路（1）包括谐振隧穿晶体管（11）和串联连接的电阻器（13）。 谐振隧穿晶体管具有超晶格结构，并且可以是谐振隧穿热电子晶体管或谐振隧穿双极晶体管。 谐振隧穿晶体管可操作以响应于基极电压（第一，第二或第三值）中的至少三个不同电流值之一流过集电极和发射极之间的电流 VIN）在第一，第二或第三值的三个不同电压值之一中。 第三电流值位于第一和第二电流值之间，第二电压值位于第一和第三电压值之间。 响应于施加到逻辑电路的信号，逻辑电路输出具有高值，低值和大约在高值和低值之间的值的至少三个状态中的一个，该信号具有第一 到第三电压值。

    Semiconductor memory device and method for producing the same
    42.
    发明公开
    Semiconductor memory device and method for producing the same 失效
    半导体存储器件及其制造方法

    公开(公告)号：EP0187596A3

    公开(公告)日：1987-01-07

    申请号：EP85402574

    申请日：1985-12-20

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao

    IPC分类号： H01L27/10 ,  H01L21/82

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： A semiconductor memory device including a semiconductor substrate (1) comprising a field oxide layer (10) selectively formed on the semiconductor substrate, a capacitor including a insulating layer (7) formed on the surface of a trench (6) formed in such a manner that at least an edge portion of the field oxide layer is removed, a conductive layer (8) formed on the insulating layer (7), a dielectric layer (9) formed on the conductive layer (8) and an electrode (11) formed on the dielectric layer (9).

    Semiconductor memory device
    43.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0098165A3

    公开(公告)日：1986-10-08

    申请号：EP83303762

    申请日：1983-06-29

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao

    IPC分类号： H01L29/06 ,  H01L29/60 ,  H01L27/10

    CPC分类号： H01L21/74 ,  H01L23/556 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The soft-error rate in an MOS d-RAM semiconductor memory device can be reduced by an impurity-doped getter region (14) of conductivity opposite to that of a substrate 11, formed in the substrate 11 below and in contact with a field oxide layer 12 on the substrate 11. This getter region 14 collects minority carriers produced by incident radiation and so shields the memory cell capacitor from these minority carriers as well as by forming a capacitor storage on the field oxide layer 12. This device has an advantage of not decreasing the density of a memory cell array.

    摘要翻译： MOS d-RAM半导体存储器件中的软错误率可以通过导电率与衬底11的导电率相反的杂质掺杂吸气剂区域（14）来降低，所述杂质掺杂吸气剂区域（14）形成在衬底11下方并且与场氧化物 该吸气区14收集由入射辐射产生的少数载流子，从而将存储器单元电容器与这些少数载流子屏蔽起来，并且通过在场氧化层12上形成电容器存储。该器件的优点在于： 不会降低存储单元阵列的密度。

    Semiconductor memory device
    44.
    发明公开
    Semiconductor memory device 失效
    半导体存储装置。

    公开(公告)号：EP0098165A2

    公开(公告)日：1984-01-11

    申请号：EP83303762.5

    申请日：1983-06-29

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao

    IPC分类号： H01L29/06 ,  H01L29/60 ,  H01L27/10

    CPC分类号： H01L21/74 ,  H01L23/556 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The soft-error rate in an MOS d-RAM semiconductor memory device can be reduced by an impurity-doped getter region (14) of conductivity opposite to that of a substrate 11, formed in the substrate 11 below and in contact with a field oxide layer 12 on the substrate 11. This getter region 14 collects minority carriers produced by incident radiation and so shields the memory cell capacitor from these minority carriers as well as by forming a capacitor storage on the field oxide layer 12. This device has an advantage of not decreasing the density of a memory cell array.

    Semiconductor memory device
    45.
    发明公开
    Semiconductor memory device 失效
    Halbleiterspeicherschaltung

    公开(公告)号：EP1603136A2

    公开(公告)日：2005-12-07

    申请号：EP05017186.7

    申请日：1998-06-03

    申请人： FUJITSU LIMITED

    发明人： Fujioka, Shinya ,  Taguchi, Masao ,  Fujieda, Waichirou ,  Sato, Yasuharu ,  Susuki, Takaaki ,  Aikawa, Tadao ,  Nagasawa, Takayuki

    IPC分类号： G11C11/4091

    CPC分类号： G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

    摘要： A semiconductor memory device comprising: a memory cell array block (150) including a plurality of sub memory cell array blocks (162); a sense amplifier column associated with said memory cell array block, the sense amplifier column including a plurality of sense amplifier blocks (164), each associated with corresponding sub memory cell array block; a column decoder receiving a column address to output a column block select signal; and a sense amplifier driving signal generating circuit for driving specified sense amplifier block among the plurality of sense amplifier blocks (164) in response to said column block select signal.

    摘要翻译： 一种半导体存储器件，包括：包括多个子存储单元阵列块（162）的存储单元阵列块（150）; 与所述存储单元阵列块相关联的读出放大器列，所述读出放大器列包括多个读出放大器块（164），每个读出放大器列与对应的子存储单元阵列块相关联; 接收列地址以输出列块选择信号的列解码器; 以及用于响应于所述列块选择信号而驱动多个读出放大器块（164）中的指定读出放大器块的读出放大器驱动信号发生电路。

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    48.
    发明公开
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
    Halbleitervorrichtung mitkomplementäremTakt und Schaltung zur Detektion des Eingangssignalzustandesdafür

    公开(公告)号：EP0878908A3

    公开(公告)日：1999-01-20

    申请号：EP97307632.6

    申请日：1997-09-29

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao ,  Tomita, Hiroyoshi ,  Matsuzaki, Yasurou

    IPC分类号： H03K5/151 ,  G11C7/00

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) (11) is supplied with a first eternal clock (CLK) and outputs a first internal clock (CLK1). A second clock input circuit (buffer) (12) is supplied with a second external clock (/CLK) complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit (22) generates a 1/2 phase shift signal 180° out of phase with the first internal clock (CLK). A second external clock state detection circuit judges whether the second external clock (/CLK) is input to the second clock input buffer. A switch (23) is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.

    摘要翻译： 公开了一种半导体器件，用于从外部时钟产生彼此互补的第一和第二内部时钟，并且可用于使用互补时钟的类型的系统和内部产生180°相位时钟的系统的系统。 第一时钟输入电路（缓冲器）（11）被提供有第一永久时钟（CLK）并输出第一内部时钟（CLK1）。 第二时钟输入电路（缓冲器）（12）被提供有与第一外部时钟互补的第二外部时钟（/ CLK）并输出第二时钟。 1/2相位时钟发生电路（22）产生与第一内部时钟（CLK）180°异相的1/2相移信号。 第二外部时钟状态检测电路判断第二外部时钟（/ CLK）是否输入到第二时钟输入缓冲器。 当输入第二外部时钟时，开关（23）被操作以产生第二时钟作为第二内部时钟，并且当不输入第二外部时钟时产生1/2相移信号作为第二内部时钟 在第二外部时钟状态检测电路上判断。

    Semiconductor device using complementary clock and signal input state detection circuit used for the same
    49.
    发明公开
    Semiconductor device using complementary clock and signal input state detection circuit used for the same 失效
    具有用于检测所述输入信号状态的互补时钟和电路的半导体装置

    公开(公告)号：EP0878908A2

    公开(公告)日：1998-11-18

    申请号：EP97307632.6

    申请日：1997-09-29

    申请人： FUJITSU LIMITED

    发明人： Taguchi, Masao ,  Tomita, Hiroyoshi ,  Matsuzaki, Yasurou

    IPC分类号： H03K5/151 ,  G11C7/00

    CPC分类号： H03L7/0805 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/135 ,  H03K5/151 ,  H03K2005/00234 ,  H03L7/0814

    摘要： A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) (11) is supplied with a first eternal clock (CLK) and outputs a first internal clock (CLK1). A second clock input circuit (buffer) (12) is supplied with a second external clock (/CLK) complementary with the first external clock and outputs a second clock. A 1/2 phase clock generating circuit (22) generates a 1/2 phase shift signal 180° out of phase with the first internal clock (CLK). A second external clock state detection circuit judges whether the second external clock (/CLK) is input to the second clock input buffer. A switch (23) is operated to produce the second clock as the second internal clock when the second external clock is input and to produce the 1/2 phase shift signal as the second internal clock when the second external clock is not input, in accordance with the judgement at the second external clock state detection circuit.