公开(公告)号：EP3350690A1

公开(公告)日：2018-07-25

申请号：EP16775908.3

申请日：2016-09-13

申请人： Microsoft Technology Licensing, LLC

发明人： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3350684A1

公开(公告)日：2018-07-25

申请号：EP16775909.1

申请日：2016-09-13

申请人： Microsoft Technology Licensing, LLC

发明人： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3345088A1

公开(公告)日：2018-07-11

申请号：EP16775911.7

申请日：2016-09-13

申请人： Microsoft Technology Licensing, LLC

发明人： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/345

CPC分类号： G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP2856313B1

公开(公告)日：2018-07-11

申请号：EP13793168.9

申请日：2013-05-23

申请人： Smith, Roger

发明人： Smith, Roger

IPC分类号： G06F11/07 ,  G06F11/14 ,  G06F11/20

CPC分类号： G06F15/825 ,  G06F7/76 ,  G06F11/00 ,  G06F11/1484 ,  G06F11/2002 ,  G06F12/0875 ,  G06F15/76 ,  G06F2015/765 ,  G06F2212/452

摘要： A fault-tolerant computer system architecture includes two types of operating domains: a conventional first domain (DID) that processes data and instructions, and a novel second domain (MM domain) which includes mentor processors for mentoring the DID according to “meta information” which includes but is not limited to data, algorithms and protective rule sets. The term “mentoring” (as defined herein below) refers to, among other things, applying and using meta information to enforce rule sets and/or dynamically erecting abstractions and virtualizations by which resources in the DID are shuffled around for, inter alia, efficiency and fault correction. Meta Mentor processors create systems and sub-systems by means of fault tolerant mentor switches that route signals to and from hardware and software entities. The systems and sub-systems created are distinct sub-architectures and unique configurations that may be operated as separately or concurrently as defined by the executing processes.

公开(公告)号：EP3198729A4

公开(公告)日：2018-06-13

申请号：EP15843355

申请日：2015-08-24

申请人： INTEL CORP

发明人： GOPAL VINODH ,  GULLEY SEAN M ,  GUILFORD JAMES D

IPC分类号： H03M7/30

CPC分类号： H03M7/3086 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/065 ,  G06F3/0673 ,  G06F9/3818 ,  G06F9/3863 ,  G06F12/023 ,  G06F12/0875 ,  G06F2212/1044 ,  G06F2212/452 ,  H03M7/3091 ,  H03M7/6005 ,  H03M7/6017

摘要： Technologies for data decompression include a computing device that reads a symbol tag byte from an input stream. The computing device determines whether the symbol can be decoded using a fast-path routine, and if not, executes a slow-path routine to decompress the symbol. The slow-path routine may include data-dependent branch instructions that may be unpredictable using branch prediction hardware. For the fast-path routine, the computing device determines a next symbol increment value, a literal increment value, a data length, and an offset based on the tag byte, without executing an unpredictable branch instruction. The computing device sets a source pointer to either literal data or reference data as a function of the tag byte, without executing an unpredictable branch instruction. The computing device may set the source pointer using a conditional move instruction. The computing device copies the data and processes remaining symbols. Other embodiments are described and claimed.

公开(公告)号：EP2831693B1

公开(公告)日：2018-06-13

申请号：EP12873212.0

申请日：2012-03-30

申请人： Intel Corporation

发明人： WEISSMANN, Eliezer ,  VAITHIANATHAN, Karthikeyan Karthik ,  ZACH, Yoav ,  GINZBURG, Boris ,  RONEN, Ronny

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F12/10 ,  G06F13/14 ,  G06F9/38 ,  G06F12/14 ,  G06F12/1027 ,  G06F12/1072 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1081

CPC分类号： G06F9/3851 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：EP3321810A1

公开(公告)日：2018-05-16

申请号：EP16203899.6

申请日：2016-12-13

申请人： VIA Alliance Semiconductor Co., Ltd.

发明人： BEAN, Brent

IPC分类号： G06F12/0855 ,  G06F12/0882 ,  G06F12/0895 ,  G06F12/0862 ,  G06F9/38 ,  G06F12/1045

CPC分类号： G06F12/023 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3814 ,  G06F12/0855 ,  G06F12/0859 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0895 ,  G06F12/1054 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/452 ,  G06F2212/601 ,  G06F2212/6022 ,  G06F2212/6026

摘要： A method of retiring cache lines from a response buffer array to an icache array of a processor including providing sequential addresses to the icache array and to a response buffer array during successive clock cycles, detecting a first address hitting the response buffer array during a first clock cycle, during a second clock cycle that follows the first clock cycle, performing a first zero clock retire to write a first cache line from the response buffer array to the icache array, and during the second clock cycle, bypassing a second address which is one of the sequential addresses. The second address is bypassed given the assumption that it will likely hit the response buffer array in a subsequent cycle. If the second address missed the response buffer array, the bypassed address is replayed with a slight time penalty, which is outweighed by the time savings of zero clock retires.

摘要翻译： 一种将高速缓存线从响应缓冲器阵列撤回到处理器的icache阵列的方法，包括在连续时钟周期期间向icache阵列和响应缓冲器阵列提供连续地址，检测在第一时钟期间击中响应缓冲器阵列的第一地址 在第一时钟周期之后的第二时钟周期期间，执行第一零时钟休眠以将第一高速缓存线从响应缓冲器阵列写入到ICache阵列，并且在第二时钟周期期间，绕过第一时钟周期的第二地址 的顺序地址。 考虑到它可能会在后续周期中响应响应缓冲区阵列，第二个地址被绕过。 如果第二个地址错过了响应缓冲区阵列，则绕过的地址会被重播并带有轻微的时间损失，这可以通过零时钟退休时间的节省超过。

公开(公告)号：EP3314405A1

公开(公告)日：2018-05-02

申请号：EP16742072.8

申请日：2016-06-23

申请人： Microsoft Technology Licensing, LLC

发明人： BURGER, Douglas C. ,  SMITH, Aaron ,  GRAY, Jan

IPC分类号： G06F9/38

CPC分类号： G06F9/30181 ,  G06F9/3814 ,  G06F9/3836 ,  G06F12/0875 ,  G06F2212/452

摘要： A processor core in an instruction block-based microarchitecture utilizes instruction blocks having headers that include an index to a size table that may be expressed using one of memory, register, logic, or code stream. A control unit in the processor core determines how many instructions to fetch for a current instruction block for mapping into an instruction window based on the block size that is indicated from the size table. As instruction block sizes are often unevenly distributed for a given program, utilization of the size table enables more flexibility in matching instruction blocks to the sizes of available slots in the instruction window as compared to arrangements in which instruction blocks have a fixed sized or are sized with less granularity. Such flexibility may enable denser instruction packing which increases overall processing efficiency by reducing the number of nops (no operations, such as null functions) in a given instruction block.

公开(公告)号：EP3198466A4

公开(公告)日：2018-04-18

申请号：EP14902388

申请日：2014-09-25

申请人： INTEL CORP

发明人： LUO SAI ,  NGAI TIN FOOK ,  CHEN HU ,  ZHOU XIAOCHENG ,  LIN CHUNXIAO ,  ZHAO KANG

IPC分类号： G06F15/167 ,  G06F9/52 ,  G06F11/36

CPC分类号： G06F12/0842 ,  G06F9/00 ,  G06F11/36 ,  G06F11/3632 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/452 ,  G06F2212/621

摘要： A processing device includes a processing core, coupled to a memory, to execute a task including a code segment identified as being monitored and a kernel recorder, coupled to the processing core via a core interface. The kernel recorder includes a first filter circuit to responsive to determining that the task being executed enters the code segment, set the kernel recorder to a first mode under which the kernel recorder is to record, in a first record, a plurality of memory addresses accessed by the code segment, and responsive to determining that the execution of the task exits the code segment, set the kernel recorder to a second mode under which the kernel recorder is to detect a write operation to a memory address recorded in the first record and record the memory address in a second record.

公开(公告)号：EP3274816A1

公开(公告)日：2018-01-31

申请号：EP16773615.6

申请日：2016-02-05

申请人： Intel Corporation

发明人： BEN-KIKI, Oren ,  PARDO, Ilan ,  ROBISON, Arch D. ,  COWNIE, James H.

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3822 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3806 ,  G06F9/3851 ,  G06F9/3877 ,  G06F9/4843 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/6028

摘要： A processor of an aspect includes a plurality of processor elements, and a first processor element. The first processor element may perform a user-level fork instruction of a software thread. The first processor element may include a decoder to decode the user-level fork instruction. The user-level fork instruction is to indicate at least one instruction address. The first processor element may also include a user-level thread fork module. The user-level fork module, in response to the user-level fork instruction being decoded, may configure each of the plurality of processor elements to perform instructions in parallel. Other processors, methods, systems, and instructions are disclosed.