WAFER WITH SCRIBE LANES COMPRISING EXTERNAL PADS AND/OR ACTIVE CIRCUITS FOR DIE TESTING
    54.
    发明授权
    WAFER WITH SCRIBE LANES COMPRISING EXTERNAL PADS AND/OR ACTIVE CIRCUITS FOR DIE TESTING 有权
    写作WAFER与外部焊盘和/或有源电路MATRIZENPRÜFENTRACKS

    公开(公告)号:EP1932176B1

    公开(公告)日:2011-11-16

    申请号:EP06809399.6

    申请日:2006-09-25

    申请人: NXP B.V.

    IPC分类号: H01L23/544 H01L23/58

    摘要: A wafer (W) comprises i) at least one independent die (D1, D2) having internal integrated components (IC), a multiplicity of internal pads (IP1-IP3) connected to some of the internal integrated components (IC), ii) scribe lanes (SL) defined between and around each independent die (Di), and in part of which are defined, for each die (D1, D2), at least a first group (G11, G12) of external pads (EP1-EP3) and/or a second group of external test integrated components (EC). The external pads (EP1-EP3) of each first group (G11, G12) are connected, through conductive tracks, to a chosen one of the internal pads (IP1-IP3) and/or internal integrated components (IC) of the associated die (D1, D2), and arranged to be fed with chosen test signals or to collect test result signals. Each external test integrated components of each second group is connected, through conductive tracks, to a chosen one of the die internal pads and/or die internal integrated components (IC) and/or to external pads of a first group.

    METAL INTERCONNECTS FOR IMAGE SENSORS
    58.
    发明授权
    METAL INTERCONNECTS FOR IMAGE SENSORS 有权
    金属化合物是图像传感器

    公开(公告)号:EP1751799B1

    公开(公告)日:2011-04-27

    申请号:EP05756194.6

    申请日:2005-06-02

    IPC分类号: H01L23/58 H01L23/485

    摘要: An integrated circuit includes a substrate; a sealing element spanning a periphery of the substrate that forms a protective boundary for the substrate; a plurality of copper lines spanning the substrate in at least two distinct layers contained within the protective boundary; a first conducting element disposed outside the sealing element; and one or more second conducting elements connecting at least two of the copper lines and that spans the sealing element; wherein the conducting elements are substantially non-oxidizing metals that are resistant to oxidization and that connect the copper line to the first conducting element.

    Method to provide a protective layer on an integrated circuit and integrated circuit fabricated according to said method
    60.
    发明公开
    Method to provide a protective layer on an integrated circuit and integrated circuit fabricated according to said method 审中-公开
    提供在集成电路的保护层的方法和集成电路,其是根据该方法制造

    公开(公告)号:EP2290684A1

    公开(公告)日:2011-03-02

    申请号:EP09169154.3

    申请日:2009-09-01

    申请人: Microdul AG

    摘要: A method to provide at least one protective, especially a light-shielding, layer (2) on an integrated circuit (10) applies the protective metal layer (2) as an additional layer to the integrated circuit (10) after completion of the integrated circuit manufacturing step. This allows for an at least partly shielded integrated circuit comprising a protective layer (2,4), wherein the metallic shielding layer (2) and the overlying polyimide layer (4) are patterned with a different, coarser resolution than the other IC metal interconnection layers.

    摘要翻译: (2)作为附加的层,以在集成电路(10)的集成完成之后的方法,(2)上的集成电路提供至少一个保护性的,爱尤其遮光,层(10)适用于保护金属层 电路的制造步骤。 这允许用于在至少部分地屏蔽集成电路,包括一个保护层(2.4),所述worin金属屏蔽层(2)和上覆的聚酰亚胺层(4)与比其它IC金属互连不同的,粗糙的分辨率图案化 层。