-
公开(公告)号：EP0284624B1
公开(公告)日：1993-08-04
申请号：EP87906695.9
申请日：1987-09-14
CPC分类号： H01L24/75 , H01L23/5385 , H01L23/5387 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/2402 , H01L2224/24137 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/75315 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15787 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A multichip integrated circuit package comprises a substrate (10) to which is affixed one or more integrated circuit chips (15a, 15b, 15c) having interconnection pads (16). A polymer film (20) overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization (25) which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.
-
2.发明公开METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT CHIPS EMPLOYING A POLYMER FILM OVERLAY LAYER 失效和装置用高分子膜表面覆盖层包装处理集成电路芯片。
公开(公告)号：EP0290501A1
公开(公告)日：1988-11-17
申请号：EP87906964.0
申请日：1987-09-28
CPC分类号： H01L24/83 , H01L21/56 , H01L21/67121 , H01L23/3164 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/76 , H01L24/82 , H01L2224/2402 , H01L2224/2919 , H01L2224/29298 , H01L2224/83192 , H01L2224/8385 , H01L2924/00011 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929
摘要： Procédé et dispositif permettant de déposer un film polymère (35) sur un substrat de forme irrégulière à des températures relativement élevées. Le procédé et le dispositif ci-décrits permettent notamment de réaliser un système d'emballage de puces à circuits intégrés à très grande échelle (33). Le système ci-décrit résout notamment les problèmes posés par le traitement à haute température et par les surfaces très irrégulières qui en résultent. Le produit résultant peut être façonné de manière à obtenir des systèmes de puces à circuits intégrés pouvant être essayés indépendamment et pouvant être reconfigurés après le test, par l'élimination du film polymère.
-
3.发明公开METHOD AND CONFIGURATION FOR TESTING ELECTRONIC CIRCUITS AND INTEGRATED CIRCUIT CHIPS USING A REMOVABLE OVERLAY LAYER 失效方法和设备测试电子电路和集成电路芯片表面覆盖层可拆卸。
公开(公告)号：EP0286660A1
公开(公告)日：1988-10-19
申请号：EP87906629.0
申请日：1987-09-28
CPC分类号： G01R31/31723 , G01R1/0408
摘要： On utilise une couche amovible de recouvrement (50), avec son motif associé de métallisation pour obtenir de manière efficace l'intégration de plaquettes de circuits imprimés à l'échelle de la plaquette gauffrée. Ce procédé et cette configuration permettent de fabriquer et de contrôler des systèmes qui seraient autrement impossibles à contrôler. La présente invention permet également de contrôler des systèmes à circuits intégrés (15) dans leur configuration finale en termes de vitesse et d'environnement de travail, en éliminant de nombreux problèmes associés aux sondes de plaquettes simples ou gauffrées. L'invention utilise également des plaquettes spéciales de contrôle (14) fixées de manière temporaire ou permanente à un paquet de plaquettes de circuits imprimés.
-
公开(公告)号：EP0920711A1
公开(公告)日：1999-06-09
申请号：EP97952567.0
申请日：1997-12-19
CPC分类号： H01L24/02 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L2224/0401 , H01L2224/16225 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01021 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3511 , H05K3/326 , H05K3/3436 , H05K3/4092 , H05K2201/0373 , H05K2201/10257 , H05K2201/10378 , Y02P70/613 , Y10S428/901 , Y10T29/49124 , Y10T29/4913 , Y10T428/24917 , H01L2924/00
摘要： An interface includes floating pad metallization (30 or 630) patterned over a dielectric interface layer with a first portion forming a central pad (26 or 626) and a second portion forming an extension (28 or 628) from the central pad extending into an interface via. Another interface includes a floating contact structure including electrically conductive material (214) coating a hole with at least some of the floating pad metallization forming an extension (216) from the hole. A conductive contact area interface includes at least one interface structure (22, 24, 26, 28, or 30) coupled between first and second contact areas (112 and 118) and including an electrical conductor having a partially open interior to form a compliant joint between the first and second contact areas.
-
5.发明授权METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT CHIPS EMPLOYING A POLYMER FILM OVERLAY LAYER 失效用于包装聚合物膜覆盖层的集成电路板的方法和装置
公开(公告)号：EP0290501B1
公开(公告)日：1993-03-10
申请号：EP87906964.9
申请日：1987-09-28
CPC分类号： H01L24/83 , H01L21/56 , H01L21/67121 , H01L23/3164 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/76 , H01L24/82 , H01L2224/2402 , H01L2224/2919 , H01L2224/29298 , H01L2224/83192 , H01L2224/8385 , H01L2924/00011 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929
摘要： A method and apparatus for disposing a polymer film (35) on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale integrated circuit chips (33). The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.
-
6.发明授权METHOD AND CONFIGURATION FOR TESTING ELECTRONIC CIRCUITS AND INTEGRATED CIRCUIT CHIPS USING A REMOVABLE OVERLAY LAYER 失效使用可拆卸覆盖层测试电子电路和集成电路板的方法和配置
公开(公告)号：EP0286660B1
公开(公告)日：1992-03-04
申请号：EP87906629.8
申请日：1987-09-28
CPC分类号： G01R31/31723 , G01R1/0408
摘要： The utilization of a removable overlay layer (50) together with its associated metallization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuits systems (15) to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips (14) which are either temporarily or permanently affixed in an integrated circuit chip package.
-
公开(公告)号：EP0432259A1
公开(公告)日：1991-06-19
申请号：EP90911255.0
申请日：1990-06-12
CPC分类号： H01L23/562 , H01L23/4985 , H01L23/5389 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/75 , H01L24/82 , H01L2224/05554 , H01L2224/2402 , H01L2224/24227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73265 , H01L2224/73267 , H01L2224/75315 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/16195 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A high acceleration object includes an electronic system which is operable at accelerations in excess of 20,000g. Connections between integrated circuit chips (130) and other portions of the electronic system are provided by metallization patterns (168) disposed on polymer dielectric layers (164) which are self-supporting across gaps (143) between components. A high density interconnect structure is disposed within the cavity of a hermetically sealed package (140).
-
8.发明公开INTEGRATED CIRCUIT PACKAGING CONFIGURATION FOR RAPID CUSTOMIZED DESIGN AND UNIQUE TEST CAPABILITY 失效更快的适应性和独特的测试可能性的集成电路封装。
公开(公告)号：EP0283515A1
公开(公告)日：1988-09-28
申请号：EP87907691.0
申请日：1987-09-28
CPC分类号： G01R31/318505 , H01L23/5382 , H01L2924/0002 , Y10T29/4913 , H01L2924/00
摘要： On utilise dans la présente invention un procédé d'interconnexion à haute densité afin de tirer profit d'une configuration de modules, dans laquelle il est possible de réaliser une architecture entièrement personnalisée d'un module de puces de circuits intégrés dans une seule couche de métallisation. On place les puces (10) des circuits intégrés de façon à tirer profit au maximum d'une couche de connexions qui comprend plusieurs configurations de conducteurs périodiquement interrompues (30). L'ensemble de l'architecture personnalisée se présente sous la forme d'une seule couche qui peut être fabriquée et produite facilement en un seul jour, ce qui permet un délai d'exécution extrêmement rapide de la conception de systèmes de circuits intégrés complexes, tels que notamment les systèmes construits à partir de composants de circuits intégrés immédiatement disponibles, à savoir microprocesseurs, puces de mémoire à accès sélectif, décodeurs et autres. Est également décrit un circuit intégré permettant de tirer profit au maximum des aptitutes aux tests rendues possibles par le système d'interconnexions à haute densité.
-
9.发明授权
公开(公告)号：EP0710430B1
公开(公告)日：2004-11-24
申请号：EP95920427.2
申请日：1995-05-15
发明人： WOJNAROWSKI, Robert, John , COLE, Herbert, Stanley , SITNIK-NIETERS, Theresa, Ann , DAUM, Wolfgang
IPC分类号： H05K1/03 , H01L23/532 , H01L23/538
CPC分类号： H05K1/0313 , H01L21/481 , H01L23/49894 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/2402 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01052 , H01L2924/01074 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/3011 , H05K1/024 , H05K1/0373 , H05K3/0032 , H05K3/386 , H05K2201/0116 , H05K2201/015 , H05K2201/0158 , H05K2203/083 , H05K2203/122 , Y10S521/918 , Y10T29/49124 , Y10T29/49155 , H01L2924/00
摘要： A method for processing a low dielectric constant material includes dispersing an additive material in a porous low dielectric constant layer, fabricating a desired electronic structure, and then removing the additive material from the pores of the low dielectric constant layer. The removal of the additive material from the pores can be accomplished by sublimation, evaporation, and diffusion. Applications for the low dielectric constant layer include the use as an overlay layer (20a) for interconnecting a circuit chip (14) supported by a substrate (10) and the use as printed circuit board material (110).
-
10.发明公开
公开(公告)号：EP0710430A1
公开(公告)日：1996-05-08
申请号：EP95920427.0
申请日：1995-05-15
发明人： WOJNAROWSKI, Robert, John , COLE, Herbert, Stanley , SITNIK-NIETERS, Theresa, Ann , DAUM, Wolfgang
CPC分类号： H05K1/0313 , H01L21/481 , H01L23/49894 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/2402 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01052 , H01L2924/01074 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/3011 , H05K1/024 , H05K1/0373 , H05K3/0032 , H05K3/386 , H05K2201/0116 , H05K2201/015 , H05K2201/0158 , H05K2203/083 , H05K2203/122 , Y10S521/918 , Y10T29/49124 , Y10T29/49155 , H01L2924/00
摘要： A method for processing a low dielectric constant material includes dispersing an additive material in a porous low dielectric constant layer, fabricating a desired electronic structure, and then removing the additive material from the pores of the low dielectric constant layer. The removal of the additive material from the pores can be accomplished by sublimation, evaporation, and diffusion. Applications for the low dielectric constant layer include the use as an overlay layer (20a) for interconnecting a circuit chip (14) supported by a substrate (10) and the use as printed circuit board material (110).
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.013 秒)
