公开(公告)号：EP3188220A2

公开(公告)日：2017-07-05

申请号：EP16202082.0

申请日：2016-12-02

Applicant: Palo Alto Research Center, Incorporated

Inventor： NG, Tse Nga ,  MEI, Ping ,  KRUSOR, Brent S. ,  WHITING, Gregory L. ,  READY, Steven E. ,  VERES, Janos

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/48

CPC classification number: H05K1/028 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/76 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24991 ,  H01L2224/76151 ,  H01L2224/76155 ,  H01L2224/76252 ,  H01L2224/82051 ,  H01L2224/82181 ,  H01L2224/8285 ,  H01L2224/82986 ,  H05K1/0326 ,  H05K1/185 ,  H05K3/14

Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer (302A). Then an electronic circuit component (304A) is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component (304A) is positioned into contact with the tacky layer (302A). A bonding material (306A) is then deposited to a portion of the adhesive layer (302A) that is not covered by the first side of the electronic circuit component (304A), to a depth which is sufficient to cover at least a portion of the electronic circuit component (304A). The bonding material (306A) is then fixed or cured into a fixed or cured bonding material, and the tacky layer (302A) is removed. By these operations, the electronic circuit component is held in a secure attachment by the fixed or cured bonding material (306A), and circuit connections (308B) may be made.

Abstract translation: 提供用于电子电路组件的制造工艺，以形成电子组件，所述电子电路组件例如裸管芯和封装集成芯片等。 电子电路部件的表面承载电子元件，例如导电迹线和/或包括接触垫的其它构造。 形成电子组件的方法包括提供粘性层（302A）。 然后提供具有第一侧和第二侧的电子电路组件（304A），其中第一侧承载电子元件。 电子电路部件（304A）的第一侧被定位成与发粘层（302A）接触。 然后将结合材料（306A）沉积到未被电子电路部件（304A）的第一侧所覆盖的粘合剂层（302A）的一部分，深度足以覆盖至少一部分 电子电路组件（304A）。 然后将结合材料（306A）固定或固化成固定或固化的结合材料，并且去除发粘层（302A）。 通过这些操作，电子电路部件通过固定或固化的结合材料（306A）保持固定连接，并且可以形成电路连接（308B）。

公开(公告)号：EP2348525A4

公开(公告)日：2014-11-05

申请号：EP09773293

申请日：2009-06-16

Applicant: KONICA MINOLTA HOLDINGS INC

Inventor： NISHI YASUO

IPC: H01L21/3205 ,  B41J2/06 ,  B41J2/07 ,  H01L21/288 ,  H01L23/52 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K3/10

CPC classification number: B41J3/4073 ,  B41J3/407 ,  H01L24/24 ,  H01L24/76 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/24011 ,  H01L2224/24145 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/76155 ,  H01L2224/82007 ,  H01L2224/82102 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H05K3/125 ,  H05K3/403 ,  H05K2201/09845 ,  H05K2203/013 ,  H05K2203/105

公开(公告)号：EP2647269A1

公开(公告)日：2013-10-09

申请号：EP11794257.3

申请日：2011-12-02

Applicant: Nederlandse Organisatie voor toegepast- natuurwetenschappelijk onderzoek TNO

Inventor： VAN DEN BRAND, Jeroen ,  KUSTERS, Roel Henry Louis ,  DIETZEL, Andreas Heinrich

IPC: H05K3/32 ,  H01L23/00

CPC classification number: H05K3/32 ,  H01L23/4985 ,  H01L24/24 ,  H01L24/76 ,  H01L24/82 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/76155 ,  H01L2224/76261 ,  H01L2224/766 ,  H01L2224/767 ,  H01L2224/82102 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/82874 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0106 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0283 ,  H05K1/189 ,  H05K3/12 ,  H05K3/305 ,  H05K2201/10674 ,  H05K2203/107 ,  H05K2203/1469 ,  H05K2203/1545 ,  H05K2203/175 ,  Y10T29/49133 ,  Y10T29/53178 ,  H01L2924/00

Abstract: A method is presented for assembling a component (30) with a flexible substrate (10), the component having electric contacts (31). The method comprises the steps of - placing the component (30) on a first main side (11) of the substrate, - applying a machine vision step to estimate a position of the electric contacts, - depositing one or more layers (32) of an electrically conductive material or a precursor thereof, said layer extending over an area of the substrate defined by the component to laterally beyond said area, - calculating partitioning lines depending on the estimated position of the electric contacts, - partitioning the layer into mutually insulated areas (32d) by locally removing material from said layer along said partitioning lines. Also an apparatus is presented that is suitable for carrying out the method. In addition an assembly is present that can be obtained by the method and the apparatus according to the invention.

公开(公告)号：EP0290501B1

公开(公告)日：1993-03-10

申请号：EP87906964.9

申请日：1987-09-28

Applicant: GENERAL ELECTRIC COMPANY

Inventor： EICHELBERGER, Charles, William ,  WOJNAROWSKI, Robert, John ,  WELLES, Kenneth, Brakeley, II

IPC: H01L21/56 ,  H01L23/28 ,  B29C51/16

CPC classification number: H01L24/83 ,  H01L21/56 ,  H01L21/67121 ,  H01L23/3164 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/76 ,  H01L24/82 ,  H01L2224/2402 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A method and apparatus for disposing a polymer film (35) on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale integrated circuit chips (33). The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.

公开(公告)号：EP4442406A1

公开(公告)日：2024-10-09

申请号：EP24164244.6

申请日：2024-03-18

Applicant: Aledia

Inventor： LEBRUN, Hugues ,  MAYER, Frédéric

IPC: B25J7/00 ,  B25J15/00 ,  B25J15/06 ,  H01L23/00 ,  H05K13/04

CPC classification number: H05K13/041 ,  B25J7/00 ,  B25J15/0052 ,  B25J15/0625 ,  H01L24/76

Abstract: L'invention concerne un système de manipulation (1) destiné à manipuler des dispositifs micrométriques (3), le système de manipulation (1) comprenant un corps principal (10) délimitant intérieurement une chambre d'aspiration (13), des buses d'aspiration (31) comprenant un canal d'aspiration (33) débouchant d'une part vers la chambre d'aspiration (13), et d'autre part au niveau d'une extrémité de préhension (37) destinée à être mise en contact avec un dispositif micrométrique (3) ; des éléments d'obturation (51), configurés pour obturer une buse d'aspiration (31) de sorte à empêcher la préhension d'un dispositif micrométrique (3) ou pour permettre une communication fluidique entre une ouverture de préhension (o37) de l'extrémité de préhension (37) et la chambre d'aspiration (13), de sorte à permettre la préhension d'un dispositif micrométrique (3) en contact avec ladite extrémité de préhension (37).
L'invention concerne également un procédé de manipulation pour manipuler des dispositifs micrométriques (3) par un tel système de manipulation (1).

公开(公告)号：EP2839522A1

公开(公告)日：2015-02-25

申请号：EP13778001.1

申请日：2013-04-19

Applicant: Rensselaer Polytechnic Institute

Inventor： KARLICEK, Robert, F. ,  LU, James, Jian-Qiang ,  GOODWIN, Charles, Sanford ,  TKACHENKO, Anton

IPC: H01L33/48 ,  H01L33/52

CPC classification number: H01L25/50 ,  H01L21/6836 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/76 ,  H01L24/82 ,  H01L24/83 ,  H01L24/95 ,  H01L24/96 ,  H01L25/0753 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/04026 ,  H01L2224/05655 ,  H01L2224/13101 ,  H01L2224/24225 ,  H01L2224/245 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/75655 ,  H01L2224/75701 ,  H01L2224/75733 ,  H01L2224/75801 ,  H01L2224/76655 ,  H01L2224/76701 ,  H01L2224/76733 ,  H01L2224/76801 ,  H01L2224/82002 ,  H01L2224/82102 ,  H01L2224/82143 ,  H01L2224/83002 ,  H01L2224/83143 ,  H01L2224/83191 ,  H01L2224/8323 ,  H01L2224/83801 ,  H01L2224/9202 ,  H01L2224/95101 ,  H01L2224/95144 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/3511 ,  H01L2933/0066 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/83205 ,  H01L2924/00014

Abstract: Disclosed herein is a method of assembling an array of light emitting diode (LED) dies on a substrate comprising : positioning dies in fluid; exposing the dies to a magnetic force to attract the dies onto magnets that are arranged at pre-determined locations either on or near the substrate; and forming permanent connections between the dies and the substrate thereby constituting an array of LED dies on a substrate.

公开(公告)号：EP1181720B1

公开(公告)日：2007-03-14

申请号：EP00908425.2

申请日：2000-01-31

Applicant: Alien Technology Corporation

Inventor： JACOBSEN, Jeffrey, Jay ,  GENGEL, Glenn, Wilhelm ,  CRAIG, Gordon, S., W.

IPC: H01L23/538 ,  H01L21/98 ,  G02F1/167

CPC classification number: H01L24/95 ,  G02F1/133305 ,  G02F1/1345 ,  H01L23/5385 ,  H01L23/5387 ,  H01L24/24 ,  H01L24/76 ,  H01L24/82 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24227 ,  H01L2224/76155 ,  H01L2224/7665 ,  H01L2224/82102 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

Abstract: Methods and apparatus for fabricating a multiple display modular assembly. In one example of a method, a first flexible layer is coupled to a substrate, a second flexible layer is coupled to the first flexible layer, and a third flexible layer is coupled to the second flexible layer. Each of the flexible layers may be generated from a separate web-line process. In one example, one flexible layer may have a display plane with a driver backplane, a second flexible layer may have a fine interconnect, and a third flexible layer may have gross interconnect. The multiple flexible layer modular assembly may apply to either flexible or rigid displays.

公开(公告)号：EP1111662A2

公开(公告)日：2001-06-27

申请号：EP00311553.2

申请日：2000-12-21

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Saia, Richard Joseph ,  Durocher, Kevin Matthew ,  Rose, James Wilson ,  Douglas, Leonard Richard

IPC: H01L21/00

CPC classification number: H01L24/76 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  Y10T29/49131 ,  H01L2924/00

Abstract: A method and process sequence for accurately aligning (14) die (108) to interconnect metal (112) on flex substrate (100) such as polyimide flex is described. A mask (102) for via formation is first patterned (12) in a metal layer on the bottom surface of the flex substrate (100). Die attach means (104) such as die attach adhesive is then applied (13) to the top side of flex substrate (100). The bond pads (106) on die are locally, adaptively aligned (14) to the patterned metal via mask (102) on the flex (100) with high accuracy. Vias (110) down to the die bond pads (106) are then created (15) by either plasma etching or excimer laser ablation through the existing aligned metal mask (102) on the flex substrate (100), and interconnect metal (112) is then deposited (16), patterned and etched (17). As a result of this process, the flex metal interconnect artwork does not have to be customized for each die misplacement using "adaptive lithography". Lower cost commercially available lithography equipment can be used for processing, reducing capital equipment and processing cost. The method is compatible with the projected designs of the next generation die which will have bond pads on the order of 40µm in size.

公开(公告)号：EP0273703A3

公开(公告)日：1990-08-22

申请号：EP87311351.8

申请日：1987-12-23

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Eichelberger, Charles William ,  Welles, Kenneth Brakeley, II ,  Wojnarowski, Robert John

IPC: H01L21/00 ,  G03F7/23 ,  G06F15/60 ,  H05K3/00

CPC classification number: H01L24/25 ,  G03F7/704 ,  H01L21/6715 ,  H01L21/768 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/75 ,  H01L24/76 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/75 ,  H01L2224/75753 ,  H01L2224/758 ,  H01L2224/759 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  Y10S148/093 ,  Y10S430/146 ,  H01L2924/00

Abstract: An adaptive method and system are disclosed for providing high density interconnections of very large scale integrated circuits on a substrate 28. The procedure is performed in four basic steps: first an artwork representa­tion for the interconnections of the integrated circuits is generated. This artwork representation is stored in a computer data base and assumes the integrated circuits to be at predetermined ideal locations and positions on the substrate. Second, using imaging (26,38,40), the actual positions of each integrated circuit on the substrate are determined. The actual positions of the integrated circuits are compared with their ideal positions to compute an offset and rotation for each integrated circuit on the substrate. Third, the computed offsets and rotations are then used to modify the artwork representation stored in the data base to account for the actual locations and positions of the integrated circuits on the substrate. Finally, the modified artwork representation is used to drive a direct writing laser lithography system (10,12,16,18,20,22,24) that actually forms the high density interconnections of the integrated circuits on the sub­strate. The artwork representations are stored in computer data bases in vector form to minimize storage requirements. The laser beam produced by the lithography system is raster scanned on the substrate. Modulation of the laser beam is controlled by the real time conversion of the vector repre­sentation of the modified artwork to be a bit mapped rep­resentation. To assure accurate formations of the intercon­nects, a feedback alignment system (42,44,46,48) is used to accurately position the laser beam throughout its raster scan.

公开(公告)号：EP3188220A3

公开(公告)日：2017-12-13

申请号：EP16202082.0

申请日：2016-12-02

Applicant: Palo Alto Research Center, Incorporated

Inventor： NG, Tse Nga ,  MEI, Ping ,  KRUSOR, Brent S. ,  WHITING, Gregory L. ,  READY, Steven E. ,  VERES, Janos

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/48

CPC classification number: H05K1/028 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/76 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24991 ,  H01L2224/76151 ,  H01L2224/76155 ,  H01L2224/76252 ,  H01L2224/82051 ,  H01L2224/82181 ,  H01L2224/8285 ,  H01L2224/82986 ,  H05K1/0326 ,  H05K1/185 ,  H05K3/14

Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer (302A). Then an electronic circuit component (304A) is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component (304A) is positioned into contact with the tacky layer (302A). A bonding material (306A) is then deposited to a portion of the adhesive layer (302A) that is not covered by the first side of the electronic circuit component (304A), to a depth which is sufficient to cover at least a portion of the electronic circuit component (304A). The bonding material (306A) is then fixed or cured into a fixed or cured bonding material, and the tacky layer (302A) is removed. By these operations, the electronic circuit component is held in a secure attachment by the fixed or cured bonding material (306A), and circuit connections (308B) may be made.