配線基板の製造方法及び配線基板
    1.
    发明专利
    配線基板の製造方法及び配線基板 有权
    制造接线板和接线板的方法

    公开(公告)号:JP2015216293A

    公开(公告)日:2015-12-03

    申请号:JP2014099319

    申请日:2014-05-13

    Inventor: 林 貴広

    Abstract: 【課題】電子部品等の他の部品との接続信頼性が向上した配線基板の製造方法及び配線基板を提供すること。 【解決手段】本発明に係る配線基板の製造方法は、第1の絶縁層上に接続端子を含む配線層を形成する工程と、前記配線層及び前記第1の絶縁層上に第2の絶縁層を形成する工程と、前記第2の絶縁層をパターニングし、前記配線層から離間する絶縁性のダミー部を前記第1の絶縁層上に形成する工程と、前記配線層、前記ダミー部及び前記第1の絶縁層上に第3の絶縁層を形成する工程と、前記接続端子の上端側が前記第3の絶縁層から突出し、前記接続端子の下端側が前記第3の絶縁層に埋設した状態で前記接続端子を露出させる開口部を前記第3の絶縁層に形成する工程とを同順に有することを特徴とする。 【選択図】図3

    Abstract translation: 要解决的问题:提供一种制造布线板的方法,其中,其中诸如电子部件的其他电子部件的连接可靠性已经增强,并且提供了布线板。解决方案:一种制造布线板的方法 在第一绝缘层上形成包括连接端子的布线层的步骤,在布线层和第一绝缘层上形成第二绝缘层的步骤,图案化第二绝缘层的步骤,以及形成绝缘的虚拟部件, 在第一绝缘层上与布线层分离,在布线层,虚拟部分和第一绝缘层上形成第三绝缘层的步骤,以及形成用于暴露连接端子的开口的步骤,处于状态 其中连接端子的上端从第三绝缘层突出,并且连接端子的下端侧嵌入在第三绝缘层中。

    キャビティ付き基板の製造方法
    3.
    发明专利
    キャビティ付き基板の製造方法 有权
    用于制造具有孔的基板的方法

    公开(公告)号:JP2015015311A

    公开(公告)日:2015-01-22

    申请号:JP2013140101

    申请日:2013-07-03

    Abstract: 【課題】キャビティの横断面寸法及び深さにバラツキが生じ難く、しかも、内壁面及び底面に平滑性を確保できるキャビティ付き基板の製造方法を提供する。【解決手段】ベース層11に貫通孔11aを形成するステップと、貫通孔11a内に金属製のダミー部品13を挿入するステップと、貫通孔11aとダミー部品13との間の環状隙間を埋める合成樹脂製の絶縁部14を形成するステップと、ダミー部品13の下面を覆う合成樹脂製の下側絶縁層15及び19を絶縁部14と連続するようにベース層11の下面に形成するステップと、ダミー部品13の上面を覆う合成樹脂製の上側絶縁層16及び20を絶縁部14と連続するようにベース層11の上面に形成するステップと、上側絶縁層16及び20にダミー部品13の上面を露出させるための露出孔27をルーター加工によって形成するステップと、露出孔27を通じて露出したダミー部品13をエッチング加工によって除去してキャビティ28を形成するステップを備える。【選択図】図8

    Abstract translation: 要解决的问题:提供一种用于制造具有空腔的基板的方法,其中该方法不容易引起空腔的横截面尺寸和深度的变化,并且还可以确保内壁表面和底表面上的平滑度 制造具有空腔的基板的方法包括以下步骤:在基底层11中形成通孔11a; 将由金属制成的虚拟部件13插入到通孔11a中; 形成由合成树脂制成的绝缘部分14,填充通孔11a和虚拟部件13之间的圆形间隙; 在基层11的下表面上形成下绝缘层15和19,以与绝缘部分14连续,下侧绝缘层覆盖虚拟部件13的下表面并由合成树脂制成; 在基层11的上表面上形成上绝缘层16和20,以与绝缘部分14连续,覆盖虚拟部件13的上表面并由合成树脂制成的上侧绝缘层; 形成用于通过路由器处理使上侧绝缘层16和20中的虚拟部件13的上表面露出的曝光孔27; 并且通过蚀刻处理去除通过曝光孔27暴露的虚拟部件13,以形成空腔28。

    Semiconductor module
    4.
    发明专利

    公开(公告)号:JP4700114B2

    公开(公告)日:2011-06-15

    申请号:JP2009027992

    申请日:2009-02-10

    Abstract: A top panel, which is disposed to face a module board with an electronic component therebetween, includes a resin layer and a metal layer, and has an insulating characteristic. The metal layer includes a metal layer formed at a front side of the resin layer and a metal layer formed at a rear side of the resin layer. With this structure, in reflow soldering performed in mounting a semiconductor module on a main board, warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the front side of the resin layer is cancelled by warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the rear side of the resin layer, whereby warp of the top panel is eliminated. This helps prevent the electronic component adhered to the top panel with adhesive from being pressed down to or pulled up from the module board due to warp of the top panel.

    Multilayer printed wiring board, electronic device, and production method of electronic device
    6.
    发明专利
    Multilayer printed wiring board, electronic device, and production method of electronic device 有权
    多层印刷线路板,电子设备及电子设备的生产方法

    公开(公告)号:JP2009277692A

    公开(公告)日:2009-11-26

    申请号:JP2008124723

    申请日:2008-05-12

    Abstract: PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board in which a multi-layered flexible part having a signal wire is constituted to control an impedance while maintaining flexibility. SOLUTION: In this multilayer printed wiring board, in an outer or inner layer part of a plurality of rigid substrate parts 12a, 12b, a flexible substrate part 13 provided extending over the plurality of rigid substrate parts 12a, 12b so as to connect the plurality of rigid substrate parts 12a, 12b is constituted comprising signal layers l6, l12 for sending signals between the plurality of rigid substrate parts 12a, 12b, ground layers l3, l9, l15 individually formed in both sides of the signal layers l6, l12, and intermediate layers l4, l5, l7, l8, l10, l11, l13, l14 formed between the ground layer l3 in the above both sides and the signal layer l6, between the signal layer l6 and the ground layer l9 in the above both sides, between the ground layer l9 and the signal layer l12, or between the signal layer l12 and the ground layer l15 in the above both sides. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 解决的问题:提供一种多层印刷线路板,其中构成具有信号线的多层柔性部件以在保持柔性的同时控制阻抗。 解决方案:在该多层印刷电路板中,在多个刚性基板部分12a,12b的外层或内层部分中设置有延伸到多个刚性基板部分12a,12b上的柔性基板部分13,以便 连接多个刚性基板部分12a,12b,其包括信号层16,1212,用于在多个刚性基板部分12a,12b之间发送信号,分别形成在信号层16的两侧的接地层13,19和15, 以及形成在上述两侧的接地层13和信号层16之间,在上述信号层16和接地层19之间形成的中间层14,15,17,18,110,111,131,144。 两侧之间,接地层19与信号层12之间,或信号层1212与上述两侧的接地层115之间。 版权所有(C)2010,JPO&INPIT

    Boring method and boring apparatus
    7.
    发明专利
    Boring method and boring apparatus 有权
    镗孔方法和钻孔设备

    公开(公告)号:JP2007201349A

    公开(公告)日:2007-08-09

    申请号:JP2006020783

    申请日:2006-01-30

    Abstract: PROBLEM TO BE SOLVED: To improve boring precision by eliminating a moving error that is generated when a boring means moves. SOLUTION: A jig plate is provided as formed with a distance mutually between centers of two imaging holes, and a center of a jig hole with respect to the centers of the two imaging holes equally with a relation between two predetermined marks and a predetermined punching position. A moving means and a movable table are adjusted to that the centers of the two imaging holes on the jig plate can be matched with imaging centers of two imaging means, respectively. A substrate for correction placed on the jig plate is bored by a punching means, the position of the opened hole is then moved to the imaging center, an error of the center of the boring position with respect to the center of the jig hole is measured, and the position of a drill with respect to the imaging means is determined to correct that error. Regarding a printed wiring board to be bored with two predetermined marks; the movable table is operated, two predetermined reference marks are matched with the positions of the imaging centers of the two imaging means, respectively, and the printed wiring board is then bored at a predetermined position by the drill. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题:通过消除钻孔装置移动时产生的移动误差来提高钻孔精度。 解决方案:夹具板被设置成两个成像孔的中心之间相互间隔开的距离,并且相对于两个成像孔的中心相对于两个成像孔的中心的夹具孔的中心以两个预定标记和 预定冲孔位置。 调整移动装置和活动台,使夹具板上的两个成像孔的中心分别与两个成像装置的成像中心相匹配。 通过冲压装置对夹具板进行校正的基板进行钻孔,打开孔的位置然后移动到成像中心,测量钻孔位置相对于夹具孔中心的中心的误差 并且确定钻头相对于成像装置的位置以校正该误差。 关于要打印有两个预定标记的印刷电路板; 可移动工作台被操作,两个预定参考标记分别与两个成像装置的成像中心的位置相匹配,并且印刷线路板然后由钻头在预定位置钻孔。 版权所有(C)2007,JPO&INPIT

    Method and structure for reducing warpage of substrate
    8.
    发明专利
    Method and structure for reducing warpage of substrate 有权
    降低衬底温度的方法和结构

    公开(公告)号:JP2007088293A

    公开(公告)日:2007-04-05

    申请号:JP2005276640

    申请日:2005-09-22

    Abstract: PROBLEM TO BE SOLVED: To realize good soldering, high-density mounting, and reliability by reducing the warpage of a substrate when soldering electronic parts on it. SOLUTION: A warpage reducing member 5 is jointed to the portion on the rear surface of mounting region of a component 2, which is the portion of a substrate 1 where warpage is desired to be reduced, for reducing the warpage of the substrate 1 on which a plurality of components 2 and 3 are mounted. A warpage reducing member 5 comprising an opening 7 has the external dimension similar to that of the component 2, and is jointed to the substrate 1 using a jointing material 6 whose melting point is lower than a solder connection part 4 of the components 2 and 3. Mounting of the warpage reducing member 5 on the substrate 1 is performed in the process identical with a normal soldering mounting process of the component 3. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题:当焊接电子部件时,通过减少基板的翘曲来实现良好的焊接,高密度安装和可靠性。 解决方案:翘曲减小构件5连接到组件2的安装区域的后表面上的部分2的部分,该部件2是需要减小翘曲的基板1的部分,以减少基板的翘曲 1,其上安装有多个部件2和3。 包括开口7的翘曲减小构件5具有与部件2相似的外部尺寸,并且使用熔点低于部件2和3的焊料连接部4的接合材料6与基板1接合 在与基板1的正常焊接安装过程相同的过程中进行翘曲减小部件5在基板1上的安装。版权所有(C)2007,JPO&INPIT

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