公开(公告)号：JP5945243B2

公开(公告)日：2016-07-05

申请号：JP2013096884

申请日：2013-05-02

Applicant: 華為技術有限公司 ,  HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： 沈暁蘭 ,  叶青松 ,  魏孔剛

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/0218 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K3/429 ,  H05K3/4602

公开(公告)号：JP2014150103A

公开(公告)日：2014-08-21

申请号：JP2013016678

申请日：2013-01-31

Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

Inventor： KUBOTA KAZUYUKI ,  FUJII TOMOJI

IPC: H05K3/46

CPC classification number: H01L23/50 ,  H01L23/58 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2924/15321 ,  H05K1/0271 ,  H05K1/16 ,  H05K1/185 ,  H05K3/108 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/0162 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0218 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/10037 ,  H05K2201/10151 ,  H05K2203/1461 ,  H05K2203/1469

Abstract: PROBLEM TO BE SOLVED: To reduce damages of a secondary battery incorporated in a wiring board.SOLUTION: A wiring board 10 includes a board body 20 and a secondary battery 30 is incorporated in the board body 20. The board body 20 includes insulation layers 21, 22, 23. The secondary buttery 30 is buried in the second insulation layer 22. The secondary battery 30 is fixed to one main surface of the first insulation layer 21 and is covered by the second insulation layer 22. The secondary battery 30 is a component in which the cubic volume is changed by its use. For example, an all-solid thin film secondary battery is used as the secondary battery 30. A material of the second insulation layer 22 is a resin (a low rigidity resin) having rigidity lower than those of the first and third insulation layers 21, 23.

Abstract translation: 要解决的问题：减少包含在布线板中的二次电池的损坏。解决方案：布线板10包括板主体20，并且二次电池30被结合在板主体20中。板主体20包括绝缘层21 二次电池30被埋在第二绝缘层22中。二次电池30被固定到第一绝缘层21的一个主表面并被第二绝缘层22覆盖。二次电池30是 其中三次体积通过其使用而改变的组分。 例如，使用全固体薄膜二次电池作为二次电池30.第二绝缘层22的材料是刚性低于第一绝缘层21和第三绝缘层21的刚性的树脂（低刚性树脂） 23。

公开(公告)号：JP5344394B2

公开(公告)日：2013-11-20

申请号：JP2009152935

申请日：2009-06-05

Applicant: 山栄化学株式会社

Inventor： 和憲 北村 ,  幸博 古閑 ,  清 佐藤

IPC: H05K1/03 ,  C08K3/00 ,  C08L63/00 ,  C08L101/00 ,  H05K3/46

CPC classification number: H05K3/0094 ,  C08K3/013 ,  C08K2201/003 ,  C08L63/00 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T428/24917

Abstract: In a curable resin composition containing an inorganic filler, the average particle diameter of the inorganic filler is 1 μm or less and the content of the inorganic filler is 50 wt % or less. The curable resin composition can be preferably used for a halogen-free resin substrate and the like having a small load on an environment as a hole-plugging curable resin composition as well as used to provide a hole-plugging build-up printed wiring board having a via-on-via structure (in particular, a stacked via structure) having an excellent crack-resistant property, an excellent insulation/connection reliability, and the like.

公开(公告)号：JP5339384B2

公开(公告)日：2013-11-13

申请号：JP2011106074

申请日：2011-05-11

Applicant: 財團法人工業技術研究院

Inventor： チェン−ミン・スー ,  シー−シェン・ウー ,  ミン−リン・リー ,  シン−ジュー・ライ

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/33 ,  H01L23/12

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4688 ,  H05K2201/0792 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.

公开(公告)号：JP5265948B2

公开(公告)日：2013-08-14

申请号：JP2008075278

申请日：2008-03-24

Applicant: 華為技術有限公司Huawei Technologies Co.,Ltd.

Inventor： 沈暁蘭 ,  叶青松 ,  魏孔剛

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/46

CPC classification number: G06F1/16 ,  H05K1/0218 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/116 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/09627

Abstract: A printed circuit board and a design method thereof are disclosed. The design method includes: wiring signal lines on an area basis at inner layers adjacent to outer surface layers; arranging the outer surface layers with no wiring or few wirings and interconnecting the outer surface layers through through vias, so that the outer surface layers function as a primary ground; and setting parameters of a line width and a layer height to control a target impedance value. The printed circuit board includes outer surface layers and two inner layers therebetween. The inner layers adjacent to the outer surface layers are used for arranging signal lines on an area basis; and the outer surface layers are arranged with no wiring or few wirings and are interconnected as a primary ground through through vias. The invention also discloses a mainboard of a terminal product using the printed circuit board.

公开(公告)号：JP5217639B2

公开(公告)日：2013-06-19

申请号：JP2008143450

申请日：2008-05-30

Applicant: 富士通株式会社

Inventor： 英明 吉村 ,  憲司 飯田 ,  知行 阿部 ,  靖友 前原 ,  隆 中川 ,  伸 平野

IPC: H05K3/46 ,  H05K1/03

CPC classification number: H05K3/4641 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0281 ,  H05K2201/0323 ,  H05K2201/09536 ,  H05K2201/09809 ,  Y10T428/24331

公开(公告)号：JP2013038374A

公开(公告)日：2013-02-21

申请号：JP2011220865

申请日：2011-10-05

Applicant: Ibiden Co Ltd ,  イビデン株式会社

Inventor： MIKADO YUKINOBU ,  SAKAI SHUNSUKE ,  TOMIKAWA MITSUHIRO ,  FURUYA TOSHIKI

IPC: H05K3/46

CPC classification number: H05K1/185 ,  H05K3/0038 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/09854 ,  H05K2201/10015 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/4913

Abstract: PROBLEM TO BE SOLVED: To improve electrical connection reliability of a wiring board.SOLUTION: A wiring board 10 comprises: a substrate 100 (core substrate) including a first surface F1, a second surface F2 opposite to the first surface F1, a cavity R10 (opening part) penetrating from the first surface F1 to the second surface F2, and through holes 300a; and a capacitor 200 arranged in the cavity R10. The through hole 300a is filled with a conductor (through hole conductor 300b). The through hole conductor 300b is formed from a first conductor part that becomes thinner from the first surface F1 toward the second surface F2 and a second conductor part that becomes thinner from the second surface F2 toward the first surface F1. The first conductor part and the second conductor part are connected in the substrate 100.

Abstract translation: 要解决的问题：提高接线板的电连接可靠性。 布线板10包括：基板100（芯基板），包括第一表面F1，与第一表面F1相对的第二表面F2，从第一表面F1贯穿至第一表面F1的空腔R10（开口部） 第二表面F2和通孔300a; 以及布置在空腔R10中的电容器200。 通孔300a填充有导体（通孔导体300b）。 通孔导体300b由从第一面F1朝向第二面F2变薄的第一导体部和从第二面F2朝向第一面F1变薄的第二导体部形成。 第一导体部分和第二导体部分连接在基板100中。版权所有：（C）2013，JPO＆INPIT

公开(公告)号：JPWO2009147936A1

公开(公告)日：2011-10-27

申请号：JP2009529449

申请日：2009-05-13

Applicant: イビデン株式会社

Inventor： 宏徳 田中 ,  宏徳 田中

IPC: H05K3/46 ,  H05K3/00

CPC classification number: H01L24/18 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/82 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/1533 ,  H01L2924/3511 ,  H05K1/0269 ,  H05K1/188 ,  H05K3/025 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2203/0152 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/1469 ,  H05K2203/166 ,  Y10T29/4913 ,  Y10T29/49146 ,  H01L2924/00 ,  H01L2224/05599

Abstract: 【課題】電子部品を内蔵し、接続信頼性の高い多層プリント配線板の製造方法を提供する。【解決手段】金属箔12に設けた位置決めマーク14に基づき開口16aを設け半田バンプを形成するため、半田バンプ18の位置精度が高く、高い接続信頼性を備えることができる。また、ソルダーレジスト層16の開口16aに半田バンプ18を設けるため、ソルダーレジスト層がダムの働きをして半田がリフローの際に流れ出さず、ファインピンチな半田バンプ18を高い接続信頼性で形成することができる。【選択図】図7

公开(公告)号：JP4722706B2

公开(公告)日：2011-07-13

申请号：JP2005517730

申请日：2005-02-03

Applicant: イビデン株式会社

Inventor： 克幸 佐野 ,  靖 稲垣

IPC: H05K3/46 ,  H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02 ,  H05K1/05 ,  H05K3/42

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/056 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/09736 ,  H05K2201/098 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Provides an IC chip for high frequency region, particularly, packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer 34P is formed in the thickness of 30µm on a core substrate 30 and a conductive circuit 58 on an interlayer resin insulation layer 50 is formed in the thickness of 15µm. By thickening the conductive layer 34P, the volume of the conductor itself can be increased thereby decreasing its resistance. Further, by using the conductive layer 34 as a power source layer, the capacity of supply of power to an IC chip can be improved.

公开(公告)号：JP2011082472A

公开(公告)日：2011-04-21

申请号：JP2009278846

申请日：2009-12-08

Applicant: Samsung Electro-Mechanics Co Ltd ,  サムソン エレクトロ−メカニックス カンパニーリミテッド.

Inventor： KO YOUNG GWAN ,  WATANABE RYOICHI ,  LEE SANG SOO ,  PARK SE WON

IPC: H05K3/10 ,  H05K3/18 ,  H05K3/22

CPC classification number: H05K3/465 ,  H05K3/045 ,  H05K3/06 ,  H05K3/064 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2203/0353

Abstract: PROBLEM TO BE SOLVED: To provide a printed circuit board, along with a method of manufacturing the board, in which a manufacturing process can be simplified and a fine circuit pattern can be achieved as a circuit pattern can be formed simultaneously on both surfaces of a base substrate by forming a trench on both surfaces of the base substrate.
SOLUTION: The printed circuit board includes a base substrate 100, an insulating layer 110 laminated on both surfaces of the base substrate 100 where a trench 120 is formed, and a circuit layer 140 including a circuit pattern 123 and a via 125 which are formed inside the trench 120 by a plating process.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种印刷电路板，以及一种制造电路板的方法，其中可以简化制造工艺，并且可以在两者上同时形成电路图案来实现精细电路图案 通过在基底基板的两个表面上形成沟槽来形成基底基板的表面。 解决方案：印刷电路板包括基底基板100，层叠在基底基板100的形成沟槽120的两个表面上的绝缘层110和包括电路图案123和通孔125的电路层140 通过电镀工艺形成在沟槽120内。 版权所有（C）2011，JPO＆INPIT