公开(公告)号：KR101065877B1

公开(公告)日：2011-09-19

申请号：KR1020097026037

申请日：2008-05-21

Applicant: 캐논 가부시끼가이샤

Inventor： 구마꾸라수수무

IPC: H01L23/12 ,  H01L21/60 ,  H05K3/34

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/06 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09427 ,  H05K2201/10515 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613

Abstract: Provided is an electronic circuit device in which the bonding state of electrodes can be detected easily with high precision. The electronic circuit device has a stack structure in which a plurality of electronic circuit boards (1a, 1b, 100a, 100b, 100c) are stacked in three or more layers through ball electrodes (10a, 10b, 20a, 20b) bonded to electrode pads (30a, 30b, 40b, 50a, 60a), wherein the electrode pads are disposed such that transmission shaded images of a pair of the electrode pads provided between adjacent layers partially overlap each other and have a non-overlapping region in which the transmission shaded images of the pair of electrode pads are free from overlapping and such that the transmission shaded image of the non-overlapping region is at least partially free from overlapping with transmission shaded images of all the other electrode pads.

公开(公告)号：KR1020110083506A

公开(公告)日：2011-07-20

申请号：KR1020110000067

申请日：2011-01-03

Applicant: 신꼬오덴기 고교 가부시키가이샤

Inventor： 나카무라준이치 ,  고바야시가즈히로

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/544 ,  H01L21/683 ,  H01L23/00 ,  H05K1/02 ,  H05K3/20 ,  H05K3/34 ,  H05K3/46 ,  H05K3/10

CPC classification number: H05K3/10 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81132 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/351 ,  H05K1/0269 ,  H05K3/205 ,  H05K3/3436 ,  H05K3/4682 ,  H05K2201/09918 ,  H05K2203/025 ,  H05K2203/0361 ,  H05K2203/1152 ,  Y10T29/49155 ,  H01L2924/00

Abstract: PURPOSE: A wiring board including a location mark, a manufacturing method thereof, and a semiconductor package are provided to offer the semiconductor package including various electronic parts including a semiconductor ship and a chip capacitor. CONSTITUTION: A wiring board including a location mark comprises a laminated structure of a first wire layer(110), a first insulation layer(120), a second wire layer(130), a second insulation layer(140), a third wire layer, a third insulation layer, a fourth wire layer, and a solder resist layer. The second wire layer is formed on the surface of the first insulation layer. The second insulation layer covers the second insulation layer.

Abstract translation: 目的：提供包括位置标记，其制造方法和半导体封装的布线板，以提供包括包括半导体船和片式电容器在内的各种电子部件的半导体封装。 构成：包括位置标记的布线板包括第一布线层（110），第一绝缘层（120），第二布线层（130），第二绝缘层（140），第三布线层 第三绝缘层，第四导线层和阻焊层。 第二导线层形成在第一绝缘层的表面上。 第二绝缘层覆盖第二绝缘层。

公开(公告)号：KR1020110050962A

公开(公告)日：2011-05-17

申请号：KR1020090107585

申请日：2009-11-09

Applicant: 에스케이하이닉스 주식회사

Inventor： 김성철 ,  박창준

IPC: H01L23/02

CPC classification number: H01L23/488 ,  H01L24/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3511 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/0191 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/09436 ,  H05K2201/09736 ,  Y02P70/613

Abstract: PURPOSE: A printed circuit board and a semiconductor package using the same are provided to prevent a short between adjacent signal lines or a connection failure by concavely forming the upper side of a warpage compensation unit. CONSTITUTION: Connection pads are formed on one side of a body unit(110). A warpage compensation unit(120) is formed on one side of the body unit. The warpage compensation unit includes conductive patterns which are electrically connected to the connection pads and a solder resist whose thickness gradually increases from the edge to the center.

Abstract translation: 目的：提供印刷电路板和使用其的半导体封装件，以防止相邻信号线之间的短路或通过凹形地形成翘曲补偿单元的上侧而导致连接故障。 构成：连接垫形成在主体单元（110）的一侧上。 翘曲补偿单元（120）形成在主体单元的一侧。 翘曲补偿单元包括电连接到连接焊盘的导电图案和厚度从边缘逐渐增加到中心的阻焊剂。

公开(公告)号：KR1020100124217A

公开(公告)日：2010-11-26

申请号：KR1020100045924

申请日：2010-05-17

Applicant: 후지쯔 가부시끼가이샤

Inventor： 이토노부타카 ,  사카이리마코토 ,  나카다테마미

IPC: H01L21/321 ,  H01L23/12

CPC classification number: H01L23/49838 ,  H01L22/34 ,  H01L23/36 ,  H01L23/4006 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/13 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19043 ,  H05K1/0268 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09663 ,  H05K2201/10734 ,  H05K2203/162 ,  Y02P70/611

Abstract: PURPOSE: A substrate structure is provided to previously verify the connection malfunction of a protruding electrode by including a disconnection detecting unit for detecting a disconnection between a partition electrode and a connector. CONSTITUTION: A plurality of first electrodes is installed on the main surface of a first plate unit. A disconnection detecting unit(16) includes a constant voltage unit(13), an abnormality detecting circuit(14), and a light emitting diode(15). A plurality of second electrodes is installed on the main surface of a second plate unit. A plurality of soldering units is formed between the first electrodes and the second electrodes in order to electrically connect the first electrodes and the second electrodes.

Abstract translation: 目的：提供一种衬底结构，用于通过包括用于检测分隔电极和连接器之间的断开的断开检测单元预先验证突出电极的连接故障。 构成：多个第一电极安装在第一板单元的主表面上。 断开检测单元（16）包括恒压单元（13），异常检测电路（14）和发光二极管（15）。 多个第二电极安装在第二板单元的主表面上。 为了电连接第一电极和第二电极，在第一电极和第二电极之间形成多个焊接单元。

公开(公告)号：KR100980356B1

公开(公告)日：2010-09-06

申请号：KR1020047013372

申请日：2003-02-21

Applicant: 레가시 일렉트로닉스, 인크.

Inventor： 클레드직캐네쓰 ,  엥글제이슨씨

IPC: H01L25/065

CPC classification number: H05K1/141 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/144 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3436 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/09954 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01005

Abstract: 본 발명은 회로 기판 상에서 3차원의 어레이로 반도체 칩을 배치하기 위한 장치 및 방법에 관한 것이다. 임의의 IC 칩은 캐리어 위에 위치 설정될 수 있고 다른 칩은 회로 기판 상에 위치 설정될 수 있는 독특한 칩 캐리어가 개시되어 있다. 추가적으로, 상기 캐리어는, 칩들이 BGA 혹은 CSP 형태일 경우라도 이들을 시스템에서 제거할 필요 없이 캐리어의 위와 아래에 있는 IC 칩의 테스트를 행할 수 있게 해준다. 이 캐리어는 현장에서 테스트를 행할 수 있도록 노출된 테스트 포인트들을 포함한다.

Abstract translation: 公开了允许在电路板上布置三维阵列半导体芯片的装置和方法。 公开了一种独特的芯片载体，其中任何IC芯片可以在电路板上定位在另一个上。 此外，载波允许在载波上并在其下测试IC芯片，而不必将载波和芯片远离系统即使它们是BGA或CSP型。 运营商包括暴露的测试点，以便现场测试。

公开(公告)号：KR1020100075396A

公开(公告)日：2010-07-02

申请号：KR1020090128663

申请日：2009-12-22

Applicant: 교세라 가부시키가이샤

Inventor： 하리카에마사토

IPC: H05K9/00 ,  H05K3/30 ,  H01L21/60

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01057 ,  H04M1/0277 ,  H05K3/3436 ,  H05K2201/10371 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/1178 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: PURPOSE: A circuit device and an electronic device are provided, which appropriately fix the electronic component about the circuit board by establishing the fixing agent between the circuit board and electronic component. CONSTITUTION: An electronic component(30) is installed in the circuit board(12). A fixing agent(40) comprises a first part located between the circuit board and electronic component, and a second part located in the outside of the first part. A shielding member(20) is arranged around the electronic component. The shielding member comprises an opening(23) which gets near to the second part. The opening corresponds to the cutout part arranged in the circuit board of the shielding member. The cutout part is located in the part which comes into contact with the circuit board of the shielding member.

Abstract translation: 目的：提供一种电路装置和电子装置，其通过在电路板和电子部件之间建立固定剂来适当地固定电路板周围的电子部件。 构成：电子部件（30）安装在电路板（12）中。 固定剂（40）包括位于电路板和电子部件之间的第一部分和位于第一部分外部的第二部分。 屏蔽构件（20）布置在电子部件周围。 遮蔽构件包括靠近第二部分的开口（23）。 开口对应于布置在屏蔽构件的电路板中的切口部分。 切口部位于与屏蔽部件的电路基板接触的部分。

公开(公告)号：KR1020100071968A

公开(公告)日：2010-06-29

申请号：KR1020107004702

申请日：2008-08-29

Applicant: 나노포일 코퍼레이션

Inventor： 반헤르덴.데이비드 ,  루드,티모시,라이언 ,  빈센트,람지

IPC: H05K1/18 ,  H05K3/32 ,  H01L21/60

CPC classification number: H01L24/83 ,  H01L24/33 ,  H01L31/02002 ,  H01L33/62 ,  H01L2224/33104 ,  H01L2224/335 ,  H01L2224/80359 ,  H01L2224/83024 ,  H01L2224/83095 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83232 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/0203 ,  H05K1/056 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3436 ,  H05K3/3494 ,  H05K2201/10106 ,  H05K2201/10689 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10969 ,  H05K2203/0278 ,  H05K2203/0405 ,  H05K2203/1163 ,  Y02P70/613 ,  Y10S362/80 ,  H01L2924/00

Abstract: A method for bonding an LED assembly (71) or other electronic package (31) to a substrate PCB containing a heat-sink (52), which utilizes layers of reactive multilayer foil disposed between contacts (32, 34) of the electronic package 31 and the associated contact pads (55) on the supporting substrate PCB. By initiating an exothermic reaction in the reactive multilayer foil, together with an application of pressure, sufficient heat is generated between the contacts (32, 34) and the associated contact pads to melt adjacent bonding material (54) to obtain good electrically and thermally conductive bonds between the contacts 32, 34 and contact pads (55) without thermally damaging the electronic package (31), heat-sensitive components (35) associated with the electronic package (31), or other the supporting substrate PCB.

Abstract translation: 一种用于将LED组件（71）或其他电子封装（31）接合到包含散热器（52）的基板PCB的方法，其利用设置在电子封装件31的触点（32,34）之间的反应性多层箔层 和支撑衬底PCB上的相关联的接触垫（55）。 通过在反应性多层箔中引发放热反应以及施加压力，在触头（32,34）和相关的接触垫之间产生足够的热量以熔化相邻的接合材料（54）以获得良好的导电和导热 触点32,34之间的接合和接触焊盘（55），而不会热损坏电子封装（31），与电子封装（31）相关联的热敏元件（35）或其它支撑衬底PCB。

公开(公告)号：KR1020100062550A

公开(公告)日：2010-06-10

申请号：KR1020080121243

申请日：2008-12-02

Applicant: 삼성전기주식회사

Inventor： 조승현 ,  유제광 ,  장태은 ,  이상수 ,  이정우 ,  이대영 ,  이재준

IPC: H01L21/027

CPC classification number: H05K1/0209 ,  H01L21/563 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K3/285 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0209 ,  H05K2201/09045 ,  H05K2201/0959 ,  H01L24/10 ,  H01L2924/00

Abstract: PURPOSE: A package substrate including solder resist layers having patterns and a method for fabricating the same are provided to rapidly emit heat which is generated from a device by forming pattern on the solder resist layers in order to increase the surface area of the device. CONSTITUTION: An insulating layer(112) is formed on a base substrate. A circuit layer(118) is formed on one side of the insulating layer. First solder resist layers(130, 130a, 130b) include a first open unit(132b) which exposes first pad parts(118a, 118b) to the circuit layer. A pattern part is formed on the surface of the first solder resist layer. The pattern part of the first solder resist layer has a concavo-convex shape.

Abstract translation: 目的：提供包括具有图案的阻焊层的封装衬底及其制造方法，以通过在阻焊层上形成图案来快速发射由器件产生的热量，以增加器件的表面积。 构成：在基底基板上形成绝缘层（112）。 电路层（118）形成在绝缘层的一侧。 第一阻焊层（130,130a，130b）包括将第一焊盘部分（118a，118b）暴露于电路层的第一开放单元（132b）。 在第一阻焊层的表面上形成图形部分。 第一阻焊层的图案部分具有凹凸形状。

公开(公告)号：KR1020100039691A

公开(公告)日：2010-04-16

申请号：KR1020080098760

申请日：2008-10-08

Applicant: 에스케이하이닉스 주식회사

Inventor： 박신영 ,  하성권

IPC: H05K1/02 ,  H05K3/32 ,  H05K3/34

CPC classification number: H05K1/11 ,  H05K3/3436 ,  H05K3/3452

Abstract: PURPOSE: A printed circuit board and a semiconductor package using the same are provided to prevent the contamination of a ball land in a filing process by forming a mold flash prevention unit around an aperture of the printed circuit board. CONSTITUTION: A substrate body(104) has an aperture. A connection wiring(112) includes a bond finger unit, a ball land unit, and a connection wiring unit. The bond finger unit is arranged around the aperture of the substrate body. The ball land unit is separated from the bond finger unit. One end of the connection wiring unit is connected to the ball land unit. The other end of the connection wiring is connected to the bond finger unit. A mold flash prevention unit(114) is arranged on the upper side of the connection wiring unit. A solder resist(116) covers the mold flash prevention unit and a connection wiring.

Abstract translation: 目的：提供一种印刷电路板和使用其的半导体封装，以通过在印刷电路板的孔径周围形成防止闪光的单元来防止在归档过程中的污染。 构成：衬底本体（104）具有孔径。 连接布线（112）包括粘合指状单元，球形区域单元和连接布线单元。 键指单元布置在基板本体的孔周围。 球地单元与键指单元分离。 连接线单元的一端连接到球陆单元。 连接线的另一端连接到键指单元。 在连接配线单元的上侧设有防模组件（114）。 阻焊剂（116）覆盖防模组件和连接配线。

公开(公告)号：KR1020100002711A

公开(公告)日：2010-01-07

申请号：KR1020080062708

申请日：2008-06-30

Applicant: 삼성전자주식회사

Inventor： 황태주

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H05K1/186 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01078 ,  H01L2924/15165 ,  H01L2924/15311 ,  H05K1/144 ,  H05K3/007 ,  H05K3/3436 ,  H05K2201/10674 ,  H01L2924/15153

Abstract: PURPOSE: An embedded wiring board, a semiconductor package including an embedded wiring board, and a method of fabricating the same are provided to mount a semiconductor chip and a printed circuit board in a film substrate previously. CONSTITUTION: In a embedded wiring board, a semiconductor package including an embedded wiring board, and a method of fabricating the same, a printed circuit board(210) comprises a second side facing a first side and the first side having the main part. A penetrating electrode(218) passes through the printed circuit board. A semiconductor chip comprises bonding pads which are embedded in the main part of the printed circuit board, is exposed to a first face direction. Bumps are offered on the penetrating electrodes and the bonding pads exposed to the first face direction.

Abstract translation: 目的：提供一种嵌入式布线板，包括嵌入式布线板的半导体封装及其制造方法，以将半导体芯片和印刷电路板预先安装在薄膜基片中。 构成：在嵌入式布线基板中，包括嵌入布线板的半导体封装及其制造方法中，印刷电路板（210）包括面对第一侧的第二面和具有主要部分的第一侧。 穿透电极（218）穿过印刷电路板。 半导体芯片包括嵌入印刷电路板的主要部分中的接合焊盘暴露于第一面方向。 在穿透电极和暴露于第一面方向的接合焊盘上提供凸起。