公开(公告)号：US20120275207A1

公开(公告)日：2012-11-01

申请号：US13097370

申请日：2011-04-29

Applicant: Theodore W. Houston ,  Puneet Kohli ,  Amitava Chatterjee

Inventor： Theodore W. Houston ,  Puneet Kohli ,  Amitava Chatterjee

IPC: G11C11/412 ,  H01L21/8244

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207

Abstract: An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.

Abstract translation: 具有SRAM单元的集成电路包括一对交叉耦合的反相器，其中第一驱动器和负载晶体管被连接以提供第一存储节点和第二驱动器以及连接到第二存储节点的负载晶体管。 SRAM单元还包括由至少一个字线控制并分别连接在第一位线和第一存储节点之间的第一和第二通过栅极晶体管以及第二位线和第二存储节点; 其中第一驱动晶体管阈值电压不同于第二驱动晶体管阈值电压，并且第一和第二驱动器阈值电压中的一个不同于通过栅极晶体管阈值电压。 或者，第一和第二驱动晶体管的阈值电压不同于对称的通过栅极晶体管阈值电压。 另外，提供了具有SRAM单元的集成电路的制造方法。

公开(公告)号：US08053322B2

公开(公告)日：2011-11-08

申请号：US12344995

申请日：2008-12-29

Applicant: Vladimir F. Drobny ,  Amitava Chatterjee ,  Phillipp Steinmann ,  Rick Wise

Inventor： Vladimir F. Drobny ,  Amitava Chatterjee ,  Phillipp Steinmann ,  Rick Wise

IPC: H01L21/336

CPC classification number: H01L21/28123 ,  H01L21/76229 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/1087 ,  H01L29/66651

Abstract: A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface. The epitaxial comprising silicon layer is oxidized to convert at least a portion into a thermally grown silicon oxide layer, wherein the thermally grown silicon oxide layer provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges. Fabrication of the IC is then completed.

Abstract translation: 一种制造集成电路（IC）及其IC的方法，包括多个金属氧化物半导体（MOS）晶体管，其栅极电介质薄膜在沟槽隔离/半导体边缘处具有减小的栅极电介质薄化和拐角锐化，用于通常为500至5000埃厚的栅极电介质层。 该方法包括提供具有包含硅的表面的衬底。 在衬底中形成多个电介质填充沟槽隔离区。 包括表面的硅在其周边与沟槽隔离区形成沟槽隔离有源区边缘。 沉积外延硅层，其中包含硅层的外延形成在包含硅的表面上。 包含硅层的外延被氧化以将至少一部分转化成热生长的氧化硅层，其中热生长的氧化硅层为所述多个MOS晶体管中的至少一个提供至少一部分栅极电介质层。 在栅极电介质上形成图案化的栅极电极层，其中图案化的栅极电极层在沟槽隔离有源区域边缘中的至少一个上延伸。 然后完成IC的制造。

公开(公告)号：US20100274506A1

公开(公告)日：2010-10-28

申请号：US12831122

申请日：2010-07-06

Applicant: Tathagata Chatterjee ,  Amitava Chatterjee

Inventor： Tathagata Chatterjee ,  Amitava Chatterjee

IPC: G01R31/26 ,  G06F19/00

CPC classification number: G01R31/2621

Abstract: A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.

Abstract translation: 一种用于测量MOSFET中的接口陷阱的方法，包括测量在预定频率范围内各种频率的脉冲波形的电荷泵浦电流，产生所测量的电荷泵浦电流相对于预定频率范围的绘制点，确定接口总数 通过计算通过绘制点的最佳拟合线的斜率参与电荷泵浦电流的陷阱。

公开(公告)号：US20090134471A1

公开(公告)日：2009-05-28

申请号：US11944861

申请日：2007-11-26

Applicant: Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

Inventor： Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

IPC: H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Abstract translation: 一个实施例涉及包括至少一个半导体器件的集成电路。 集成电路包括与半导体器件的第一端子相关联的第一接触。 第一触点跨越介电层并且将第一端子耦合到在集成电路上水平传送信号的互连线，其中互连线具有第一组成。 集成电路还包括与半导体器件的第二端子相关联的第二触点。 第二接触跨越电介质层并将第二端子耦合到通孔连接到的着陆焊盘，其中着陆焊盘具有不同于第一组成的第二组成。 还公开了其它电路和方法。

公开(公告)号：US07314800B2

公开(公告)日：2008-01-01

申请号：US11296164

申请日：2005-12-07

Applicant: Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

Inventor： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC: H01L21/00

CPC classification number: H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract translation: 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

公开(公告)号：US20060205169A1

公开(公告)日：2006-09-14

申请号：US11074905

申请日：2005-03-08

Applicant: Jong Yoon ,  Shirin Siddiqui ,  Amitava Chatterjee ,  Brian Goodlin ,  Karen Kirmse

Inventor： Jong Yoon ,  Shirin Siddiqui ,  Amitava Chatterjee ,  Brian Goodlin ,  Karen Kirmse

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/6653

Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).

Abstract translation: 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（130），所述栅极结构（130）在其相对的侧壁上具有L形侧壁间隔物（430），并且将源极/ 漏极植入物（310或510）进入靠近栅极结构（130）的衬底（110）中。 制造半导体器件的方法还包括去除L形侧壁间隔物（430）的水平段的至少一部分。

公开(公告)号：US20060027895A1

公开(公告)日：2006-02-09

申请号：US11239794

申请日：2005-09-30

Applicant: Amitava Chatterjee

Inventor： Amitava Chatterjee

IPC: H01L31/11 ,  H01L21/3205 ,  H01L29/00

CPC classification number: H01L29/6625 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/0744 ,  H01L29/735

Abstract: A method of forming a lateral bipolar transistor without added mask in CMOS flow including a p-substrate; patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall deposit and etch and then source/drain pattern and implant for nMOS and pMOS. The method includes the steps of forming emitter and collector contacts by implants used in source/drain regions; forming an emitter that includes implants done in core pMOS during core pMOS LDD extender and pocket implant steps and while the collector omits the core pMOS LDD extender and pocket implants; forming a base region below the emitter and collector contacts by the n-well region with said base region going laterally from emitter to collector being the n-well and including pocket implants; and forming base contact by said n-well region and by implants used in nMOS source/drain regions.

公开(公告)号：US20060024910A1

公开(公告)日：2006-02-02

申请号：US10899664

申请日：2004-07-27

Applicant: Amitava Chatterjee ,  Alwin Tsao ,  Manuel Quevedo-Lopez ,  Jong Yoon ,  Shaoping Tang

Inventor： Amitava Chatterjee ,  Alwin Tsao ,  Manuel Quevedo-Lopez ,  Jong Yoon ,  Shaoping Tang

IPC: H01L21/76

CPC classification number: H01L21/76237 ,  H01L21/823878

Abstract: A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).

Abstract translation: 公开了一种形成隔离结构的方法（200），并且包括在与隔离区域相关联的半导体本体（214）中形成隔离沟槽，并用植入物掩模材料（216）填充隔离沟槽的底部。 在其底部填充有注入掩模材料之后，在隔离沟槽（218）中进行成角度的离子注入，从而在半导体本体中形成阈值电压补偿区域。 随后，隔离沟槽填充有电介质材料（220）。

公开(公告)号：US20050145949A1

公开(公告)日：2005-07-07

申请号：US11054083

申请日：2005-02-08

Applicant: Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

Inventor： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8239 ,  H01L27/02 ,  H01L27/105 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

公开(公告)号：US06869840B2

公开(公告)日：2005-03-22

申请号：US10645399

申请日：2003-08-21

Applicant: Amitava Chatterjee ,  Keith E. Kunz

Inventor： Amitava Chatterjee ,  Keith E. Kunz

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L23/62 ,  H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Electrostatic discharge (ESD) protection structures utilizing bipolar conduction are disclosed. The structures each include a parasitic p-n-p bipolar transistor (102); some of the disclosed embodiments include this transistor within a silicon-controlled-rectifier (SCR) type of ESD protection structure. A p+ doped region (116, 216, 316, 416, 516) is disposed at a surface of an n-well (112, 212, 312, 412, 512) overlying a location (115, 215, 315, 415, 515) that receives both the n-well (112, 212, 312, 412, 512) implants and also the p-well (213, 313, 413, 513) implants. Preferably, the well implants are designed to provide retrograde doping profiles. The number of net impurities is reduced, and thus the base Gummel number is lowered, at the compensated well portion (112′, 212′, 312′, 412′, 512′), resulting in improved gain for the vertical bipolar device.

Abstract translation: 公开了利用双极导电的静电放电（ESD）保护结构。 所述结构各自包括寄生p-n-p双极晶体管（102）; 一些所公开的实施例包括在硅控整流器（SCR）类型的ESD保护结构内的该晶体管。 p +掺杂区域（116,216,316,416,516）设置在覆盖位置（115,215,315,415,515）上的n阱（112,212,312,412,512）的表面上， 其接收n阱（112,212,312,412,512）植入物以及p阱（213,313,413,513）植入物。 优选地，井注入被设计成提供逆向掺杂分布。 在补偿的井部分（112'，212'，312'，412'，512'），净杂质的数量减少，从而碱基Gummel数降低，导致垂直双极器件的增益增加。