公开(公告)号：US09563938B2

公开(公告)日：2017-02-07

申请号：US14269979

申请日：2014-05-05

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Raka Singh ,  Rajesh Mahapatra ,  Gaurav Malik

IPC: G06T5/00 ,  H04N1/58 ,  H04N1/409 ,  H04N9/64 ,  G06K9/40 ,  G06T5/30

CPC classification number: G06T5/002 ,  G06K9/40 ,  G06T5/30 ,  G06T2207/20032 ,  G06T2207/20192 ,  H04N1/409 ,  H04N1/58 ,  H04N9/646

Abstract: A system and method for removing noise from images are disclosed herein. An exemplary system includes an edge-detection-based adaptive filter that identifies edge pixels and non-edge pixels in an image and selects a filtering technique for at least one non-edge pixel based on a comparison of the at least one non-edge pixel to a neighboring pixel region, wherein such comparison indicates whether the at least one non-edge pixel is a result of low-light noise.

Abstract translation: 本文公开了一种用于从图像中去除噪声的系统和方法。 一个示例性系统包括基于边缘检测的自适应滤波器，其识别图像中的边缘像素和非边缘像素，并且基于至少一个非边缘像素的比较为至少一个非边缘像素选择滤波技术 到相邻像素区域，其中这种比较指示至少一个非边缘像素是否是低光噪声的结果。

公开(公告)号：US20160104072A1

公开(公告)日：2016-04-14

申请号：US14575198

申请日：2014-12-18

Applicant: Analog Devices Technology

Inventor： Raka Singh

IPC: G06N7/00 ,  G06N5/02

CPC classification number: G06N7/005

Abstract: One factor in limiting the speed of conventional implementations of mixture models is that the algorithm involves many decisions where different operations are fetched and performed depending on the outcome of the decisions. These decisions cause flushing of the pipeline, and thus prevent the realization of a highly parallel pipeline in a processor. Without parallelism, the throughput of the pipeline in the processor, i.e., the ability to process many samples of the digital input at a time, is limited. To alleviate this issue, implementation of the mixture model is reformulated, among other things, by embedding decisions into the process flow as multiplicative factors. The resulting implementation alleviates the need to use if-else statements for the decisions and reduces the number of times the pipeline has to be flushed. The implementation enables a pipeline with a higher degree of parallelism and thereby increases throughput and speed of the implementation.

Abstract translation: 限制混合模型的常规实现速度的一个因素是，该算法涉及许多决定，其中取决于决策的结果而获取和执行不同的操作。 这些决定导致流水线的冲洗，从而防止在处理器中实现高度并行的管线。 没有并行性，处理器中的流水线的吞吐量，即一次处理数字输入的许多样本的能力受到限制。 为了缓解这个问题，混合模型的实现被重新设计，其中包括将决策嵌入过程流作为乘数因子。 所产生的实现减轻了使用if-else语句进行决策的需要，并减少了管道必须被刷新的次数。 该实现实现了具有更高并行度的管道，从而增加了实现的吞吐量和速度。

公开(公告)号：US20160049823A1

公开(公告)日：2016-02-18

申请号：US14460913

申请日：2014-08-15

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： YOSEF STEIN ,  ROMAN TROGAN ,  HAIM PRIMO

IPC: H02J7/02 ,  H04W72/04 ,  H04W4/00

CPC classification number: H02J7/025 ,  H02J50/10 ,  H04B7/0617 ,  H04W4/24 ,  H04W4/38 ,  H04W4/70 ,  H04W72/046 ,  H04W88/16

Abstract: A wireless charging platform for a wireless sensor network is disclosed, which includes a radio frequency energy distributor and data aggregator (REDDA) system configured to aggregate data from sensor nodes and wirelessly transmit power to the sensor nodes using a beamformed RF signal. The REDDA system can set a radiation pattern for the beamformed RF signal that maximizes RF energy transfer to the sensor nodes based on an environment associated with the sensor nodes. In various embodiments, the REDDA system can include an Internet of Things (IoT) interface connected to an IoT network, and the REDDA system can use information gleaned from the IoT network to set the radiation pattern.

Abstract translation: 公开了一种用于无线传感器网络的无线充电平台，其包括射频能量分配器和数据聚合器（REDDA）系统，其被配置为聚合来自传感器节点的数据并使用波束形成的RF信号将功率无线传输到传感器节点。 REDDA系统可以基于与传感器节点相关联的环境，为波束形成的RF信号设置辐射图案，使射频能量传递到传感器节点。 在各种实施例中，REDDA系统可以包括连接到IoT网络的物联网（IoT）接口，并且REDDA系统可以使用从IoT网络收集的信息来设置辐射图。

公开(公告)号：US20150363318A1

公开(公告)日：2015-12-17

申请号：US14306162

申请日：2014-06-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： JOHN L. REDFORD ,  MICHAEL G. PERKINS

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0895 ,  Y02D10/13

Abstract: In an example, a system and method are provided for predicting in which way a requested memory address is most likely to be held in a multi-way cache, based on the last way accessed by the specified address register if available. If not available, then the system may determine that no best prediction is available. In that case, each way is read, and the superfluous values are disregarded, or a cache fill is performed as necessary. In certain embodiments, only a portion of the least significant bits of an add operation are used for way prediction in base-plus-offset addressing modes. This enables the decision to be made before the full-width add is complete, so that the clock cycle length is not unnecessarily lengthened by the prediction operation.

Abstract translation: 在一个示例中，提供了一种系统和方法，用于基于由指定地址寄存器访问的最后方式（如果可用）来预测所请求的存储器地址最有可能保持在多路高速缓存中的方式。 如果不可用，则系统可以确定没有可用的最佳预测。 在这种情况下，读取每种方式，忽略多余的值，或者根据需要执行缓存填充。 在某些实施例中，只有加法运算的最低有效位的一部分用于基加 - 偏移寻址模式中的方式预测。 这使得能够在全宽加法完成之前进行判定，从而通过预测操作不会不必要地延长时钟周期长度。

公开(公告)号：US09178529B2

公开(公告)日：2015-11-03

申请号：US14057153

申请日：2013-10-18

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Yunzhi Dong ,  Hajime Shibata ,  Wenhua W. Yang ,  Richard E. Schreier

IPC: H03M3/00 ,  H03M1/00 ,  H03M1/12 ,  H04L25/06 ,  H04M1/725 ,  H03M1/14

CPC classification number: H03M3/344 ,  H03M1/00 ,  H03M1/12 ,  H03M1/144 ,  H03M1/145 ,  H03M3/30 ,  H03M3/416 ,  H04L25/067 ,  H04M1/72519

Abstract: The present disclosure describes an improved multi-stage noise shaping (MASH) analog-to-digital converter (ADC) for converting an analog input signal to a digital output signal. In particular, a full delta-sigma (ΔΣ) modulator is provided at the front-end of the MASH ADC, and another full ΔΣ modulator is provided at the back-end of the MASH ADC. The front-end ΔΣ modulator digitizes an analog input signal, and the back-end ΔΣ modulator digitizes an error between the output of the front-end ΔΣ modulator and the (original) analog input signal. In this configuration where the back-end modulator digitizes the error of the (full) front-end modulator, some design constraints of the front-end are relaxed. These design constraints include thermal noise, digital noise cancellation filter complexity (the quantization noise of the front-end is already shaped by the noise transfer function of the front-end), and/or non-linearity.

Abstract translation: 本公开描述了一种用于将模拟输入信号转换为数字输出信号的改进的多级噪声整形（MASH）模数转换器（ADC）。 特别地，在MASH ADC的前端提供了一个完整的delta-sigma（＆Dgr＆amp; Sgr）调制器，另一个完整的＆Dgr＆amp; 调制器设置在MASH ADC的后端。 前端＆Dgr＆＆ 调制器将模拟输入信号数字化，后端＆Dgr＆amp; 调制器数字化前端＆Dgr＆amp; Sgr的输出之间的误差; 调制器和（原始）模拟输入信号。 在这种配置中，后端调制器将（全）前端调制器的误差数字化，前端的一些设计约束被放宽。 这些设计约束包括热噪声，数字噪声消除滤波器复杂度（前端的量化噪声已经由前端的噪声传递函数形成）和/或非线性。

公开(公告)号：US09177383B2

公开(公告)日：2015-11-03

申请号：US14013122

申请日：2013-08-29

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Anil M. Sripadarao ,  Bijesh Poyil

IPC: G06K9/48 ,  G06T7/00 ,  G06K9/62

CPC classification number: G06T7/0085 ,  G06K9/00228 ,  G06K9/4614 ,  G06K9/6256 ,  G06K9/6267 ,  G06K9/6282

Abstract: In one aspect, there is disclosed a digital signal processor and method performed by the same for performing object detection, including facial detection, in a reduced number of clock cycles. The method comprises using Sobel edge detection to identify regions with many edges, and classifying those regions as foreground candidates. Foreground candidates are further checked for vertical or horizontal symmetry, and symmetrical windows are classified as face candidates. Viola-Jones type facial detection is then performed only on those windows identified as face candidates.

Abstract translation: 在一个方面，公开了一种数字信号处理器及其方法，该数字信号处理器和方法由减少数量的时钟周期执行，用于执行包括面部检测的对象检测。 该方法包括使用Sobel边缘检测来识别具有许多边缘的区域，并将这些区域分类为前景候选。 进一步检查前景候选者的垂直或水平对称性，对称窗口被分类为面部候选。 然后仅在被识别为面部候选的那些窗口上执行Viola-Jones型面部检测。

公开(公告)号：US20150288380A1

公开(公告)日：2015-10-08

申请号：US14302173

申请日：2014-06-11

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： JIALIN ZHAO ,  RICHARD E. SCHREIER ,  JOSE BARREIRO SILVA ,  HAJIME SHIBATA ,  WENHUA W. YANG ,  YUNZHI DONG

IPC: H03M3/00

CPC classification number: H03M3/378 ,  H03M1/1019 ,  H03M1/1038 ,  H03M1/74 ,  H03M3/37 ,  H03M3/384 ,  H03M3/388 ,  H03M3/464

Abstract: Digital-to-analog converters (DACs) are used widely in electronics. The DACs are usually not ideal and typically exhibits errors, e.g., static mismatch errors. This disclosure describes a digital calibration technique for DAC static mismatch in continuous-time delta-sigma modulators (CTDSMs). The methodology utilizes the DAC unit elements (UEs) themselves to measure each other's mismatch. There are no extra circuitries except for the logic design inside DAC drivers or comparators. The methodology is an attractive calibration technique for high performance CTDSMs, especially for high speed system in multi-gigahertz range with low over-sampling rate (OSR).

Abstract translation: 数模转换器（DAC）广泛应用于电子产品。 DAC通常不理想，并且通常表现出错误，例如静态失配错误。 本公开描述了用于连续时间Δ-Σ调制器（CTDSM）中的DAC静态失配的数字校准技术。 该方法利用DAC单元元件（UE）本身来测量彼此的不匹配。 没有额外的电路，除了DAC驱动器或比较器中的逻辑设计。 该方法是高性能CTDSM的有吸引力的校准技术，特别是对于具有低过采样率（OSR）的多千兆赫兹范围内的高速系统。

公开(公告)号：US20150180486A1

公开(公告)日：2015-06-25

申请号：US14134782

申请日：2013-12-19

Applicant: Analog Devices Technology

Inventor： Hyman Shanan ,  Michael F. Keaveney

IPC: H03L7/099 ,  H03L7/085

CPC classification number: H03L7/099 ,  H03L1/026 ,  H03L7/085 ,  H03L7/104

Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO and a calibration voltage generation circuit that can generate a calibration voltage for controlling a tuning voltage input of the VCO when the VCO is being coarsely tuned. Additionally, the calibration voltage generation circuit can sense a temperature of the PLL, and can control a voltage level of the calibration voltage to provide compensation based on the sensed temperature. The calibration voltage generation circuit can include a bandgap reference circuit configured to generate a zero-to-absolute-temperature (ZTAT) current and a proportional-to-absolute temperature (PTAT) current, and the calibration voltage can be generated based in part on a difference between the PTAT current and the ZTAT current.

Abstract translation: 提供了锁相环（PLL）的频率锁定增强的装置和方法。 在一个方面，PLL可以包括VCO和校准电压产生电路，当VCO被粗调谐时，可以产生用于控制VCO的调谐电压输入的校准电压。 此外，校准电压产生电路可以感测PLL的温度，并且可以控制校准电压的电压电平，以基于感测到的温度来提供补偿。 校准电压产生电路可以包括被配置为产生零绝对温度（ZTAT）电流和比例绝对温度（PTAT）电流的带隙基准电路，并且校准电压可以部分地基于 PTAT电流和ZTAT电流之间的差异。

公开(公告)号：US20150171880A1

公开(公告)日：2015-06-18

申请号：US14571274

申请日：2014-12-15

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Trevor Clifford Caldwell ,  Richard E. Schreier ,  David Alldred ,  Wenhua W. Yang

IPC: H03M1/06 ,  H03M1/36 ,  H03M3/00 ,  H03M1/74

CPC classification number: H03M1/0673 ,  H03M1/361 ,  H03M1/74 ,  H03M3/30 ,  H03M3/338 ,  H03M3/464

Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.

Abstract translation: 一方面，公开了一种电信号转换器。 示例性电信号转换器可以包括多个有序的转换器元件。 可以提供元素选择逻辑以伪随机选择指向开关矩阵的指针，其中开关矩阵根据逐步的“二进制二最大模式”来映射转换器元件。有利地，可以应用伪随机逐步的Δ-二最大模式 到一阶转换器和用于纠错的反馈转换器。

公开(公告)号：US20150084676A1

公开(公告)日：2015-03-26

申请号：US14034917

申请日：2013-09-24

Applicant: Analog Devices Technology

Inventor： David J. McLaurin ,  Christopher W. Angell ,  Michael F. Keaveney

IPC: H03L7/085 ,  H03L7/10

CPC classification number: H03L7/1976 ,  H03L7/085 ,  H03L7/104 ,  H03L7/199 ,  H03L7/23

Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.