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    Method for forming integrated circuits on a strained semiconductor substrate
    1.
    发明授权
    Method for forming integrated circuits on a strained semiconductor substrate 有权
    在应变半导体衬底上形成集成电路的方法

    公开(公告)号：US08906776B2

    公开(公告)日：2014-12-09

    申请号：US13240769

    申请日：2011-09-22

    Applicant: Daniel Bensahel ,  Aomar Halimaoui

    Inventor： Daniel Bensahel ,  Aomar Halimaoui

    IPC: H01L21/30 ,  H01L29/78 ,  H01L21/18 ,  H01L21/3063

    CPC classification number: H01L29/7849 ,  H01L21/187 ,  H01L21/3063 ,  H01L29/06 ,  H01L29/32 ,  H01L29/78

    Abstract: A method for forming an electronic circuit on a strained semiconductor substrate, including the steps of: forming, on a first surface of a semiconductor substrate, electronic components defining electronic chips to be sawn; and forming at least portions of a layer of a porous semiconductor material on the side of a second surface of the semiconductor substrate, opposite to the first surface, to bend the semiconductor substrate.

    Abstract translation: 一种在应变半导体衬底上形成电子电路的方法，包括以下步骤：在半导体衬底的第一表面上形成限定要锯切的电子芯片的电子部件; 以及在所述半导体衬底的与所述第一表面相对的一侧的所述一侧上形成多孔半导体材料层的至少一部分以弯曲所述半导体衬底。

    Method for making a semi-conducting substrate located on an insulation layer
    2.
    发明授权
    Method for making a semi-conducting substrate located on an insulation layer 有权
    制造位于绝缘层上的半导体衬底的方法

    公开(公告)号：US08536027B2

    公开(公告)日：2013-09-17

    申请号：US12679271

    申请日：2008-09-26

    Applicant: Aomar Halimaoui ,  Daniel Bensahel

    Inventor： Aomar Halimaoui ,  Daniel Bensahel

    IPC: H01L21/20 ,  H01L29/02

    CPC classification number: H01L29/0649 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/76262 ,  H01L21/764

    Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.

    Abstract translation: 一种用于制造在绝缘层上延伸的硅层的方法，包括以下步骤：在硅晶片的至少一部分上形成硅 - 锗层; 将硅 - 锗层的部分转变成多孔硅垫; 在硅 - 锗层和多孔硅垫上生长单晶硅层; 去除硅 - 锗层; 氧化多孔硅垫; 以及在所述硅层上沉积绝缘材料。

    Process for assembling two wafers and corresponding device
    5.
    发明授权
    Process for assembling two wafers and corresponding device 有权
    组装两片晶圆及相应装置的工艺

    公开(公告)号：US09330957B2

    公开(公告)日：2016-05-03

    申请号：US13330146

    申请日：2011-12-19

    Applicant: Aomar Halimaoui ,  Marc Zussy

    Inventor： Aomar Halimaoui ,  Marc Zussy

    IPC: H01L21/762

    CPC classification number: H01L29/0657 ,  H01L21/76251 ,  H01L29/16

    Abstract: A process for assembling a first wafer and a second wafer each bevelled on their peripheries includes excavating the bevelled peripheral part of at least one first side of the first wafer to create a deposit bordering the region excavated in the material of the first wafer. The first side and a second side of the second wafer are then bonded together.

    Abstract translation: 一种组装第一晶片和第二晶片的方法，每个在它们的周边上都是倾斜的，包括挖掘第一晶片的至少一个第一侧的斜切周边部分，以形成与在第一晶片的材料中挖出的区域接壤的沉积物。 然后将第二晶片的第一面和第二面接合在一起。

    Housing, in particular for a biofuel cell
    6.
    发明授权
    Housing, in particular for a biofuel cell 有权
    住房，特别是生物燃料电池

    公开(公告)号：US09219286B2

    公开(公告)日：2015-12-22

    申请号：US13993634

    申请日：2011-12-12

    Applicant: Pascale Mazoyer ,  Aomar Halimaoui

    Inventor： Pascale Mazoyer ,  Aomar Halimaoui

    IPC: H01M8/16 ,  H01G11/52 ,  H01G11/78 ,  H01M8/10 ,  H05K5/02

    CPC classification number: H01M8/16 ,  H01G11/52 ,  H01G11/78 ,  H01M8/1097 ,  H05K5/02 ,  Y02E60/13 ,  Y02E60/521 ,  Y02E60/527

    Abstract: A housing includes a body with a first silicon element and a second porous silicon element, at least one first cavity provided in the porous silicon element, a first electrically conducting contact area electrically coupled to at least a portion of at least one internal wall of the at least one first cavity, and a second electrically conducting contact area electrically coupled to a different portion of the at least one internal wall of the second porous silicon element of the at least one first cavity, wherein the two contact areas are electrically isolated from each other.

    Abstract translation: 壳体包括具有第一硅元件和第二多孔硅元件的主体，设置在多孔硅元件中的至少一个第一空腔，第一导电接触区域，电耦合到至少一个内壁的至少一部分 至少一个第一空腔和第二导电接触区域，其电耦合到所述至少一个第一空腔的所述第二多孔硅元件的所述至少一个内壁的不同部分，其中所述两个接触区域与所述至少一个第一空腔电绝缘 其他。

    Method for forming a localized region of a material difficult to etch
    9.
    发明申请
    Method for forming a localized region of a material difficult to etch 有权
    用于形成难以蚀刻的材料的局部区域的方法

    公开(公告)号：US20050026457A1

    公开(公告)日：2005-02-03

    申请号：US10744680

    申请日：2003-12-23

    Applicant: Aomar Halimaoui ,  Daniel Bensahel

    Inventor： Aomar Halimaoui ,  Daniel Bensahel

    IPC: H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/51 ,  H01L21/338 ,  H01L21/461

    CPC classification number: H01L21/28194 ,  H01L21/31604 ,  H01L21/31691 ,  H01L29/517 ,  H01L29/66583

    Abstract: A method for forming, in an integrated circuit, a localized region of a material difficult to etch, including the steps of forming a first silicon oxide layer having a thickness smaller than 1 nm on a silicon substrate; depositing, on the first layer, a second layer selectively etchable with respect to the first layer; forming in the second layer an opening according to the pattern of said localized region; selectively growing on the second layer, around the opening, a germanium layer, the material of the second layer being chosen to enable this selective growth, whereby there exists in the germanium an opening conformable with the above opening; depositing the material difficult to etch so that it does not deposit on the germanium; depositing a conductive layer to fill the opening in the germanium; performing a leveling to expose the germanium; and removing the germanium and the first and second layers.

    Abstract translation: 一种在集成电路中形成难以蚀刻的材料的局部区域的方法，包括在硅衬底上形成厚度小于1nm的第一氧化硅层的步骤; 在所述第一层上沉积相对于所述第一层可选择性地蚀刻的第二层; 在所述第二层中形成根据所述局部区域的图案的开口; 选择性地生长在第二层上，围绕开口，锗层，选择第二层的材料以使其能够进行选择性生长，由此在锗中存在与上述开口相适应的开口; 沉积材料难以蚀刻，使得其不沉积在锗上; 沉积导电层以填充锗中的开口; 进行平整暴露锗; 并且去除锗以及第一和第二层。

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