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    Determining noise and sound power level differences between primary and reference channels
    2.
    发明授权
    Determining noise and sound power level differences between primary and reference channels 有权

    公开(公告)号：US10127919B2

    公开(公告)日：2018-11-13

    申请号：US14938798

    申请日：2015-11-11

    申请人： Cirrus Logic Inc.

    发明人： Jan S. Erkelens

    IPC分类号： H04R29/00 ,  G10L21/0232 ,  G10L25/12 ,  G10L25/21 ,  H04R3/00

    摘要： A method for estimating a noise power level difference (NPLD) between a primary microphone and a reference microphone of an audio device includes obtaining primary and reference channels of an audio signal with primary and reference microphones of an audio device and estimating a noise magnitude of the reference channel of the audio signal to provide a noise variance estimate for one or more frequencies. A modelled probability density function (PDF) of a fast Fourier transform (FFT) coefficient of the primary channel of the audio signal is maximized to provide a NPLD between the noise variance estimate of the reference channel and a noise variance estimate of the primary channel. A modelled PDF of an FFT coefficient of the reference channel of the audio signal is maximized to provide a complex speech power level difference (SPLD) coefficient between the speech FFT coefficients of the primary and reference channel. A corrected noise magnitude of the reference channel is then calculated based on the noise variance estimate, the NPLD and the SPLD coefficient.

    Schmitt trigger with threshold voltage close to rail voltage
    3.
    发明授权
    Schmitt trigger with threshold voltage close to rail voltage 有权

    公开(公告)号：US10063218B2

    公开(公告)日：2018-08-28

    申请号：US14270296

    申请日：2014-05-05

    申请人： Cirrus Logic, Inc.

    发明人： Dan Shen

    IPC分类号： H03F99/00 ,  H03K3/037 ,  H03F3/217 ,  H03K3/3565

    CPC分类号： H03K3/0377 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2173 ,  H03K3/3565

    摘要： Voltage level shifting in a switching output stage is presented. The circuit may include a switching output stage configured to receive an analog input signal and provide a responsive digital output signal, the switching output stage having a first switching device coupled to a first supply voltage and a second switching device coupled to a second supply voltage, the first switching device and the second switching device being coupled to a common output node. The apparatus may also include a voltage level shifter circuit coupled to a switching control node of the second switching device, the voltage level shifter configured to shift a voltage level at the switching control node of the second switching device relative to the analog input signal, wherein the digital output signal at the common output node transitions as the input signal reaches a predetermined threshold value.

    Systems and methods for compressing a digital signal
    8.
    发明授权
    Systems and methods for compressing a digital signal 有权

    公开(公告)号：US09626981B2

    公开(公告)日：2017-04-18

    申请号：US14745795

    申请日：2015-06-22

    申请人： Cirrus Logic, Inc.

    发明人： Brian Parker Chesney

    IPC分类号： H04N1/405 ,  H04N1/407 ,  H04N1/00 ,  G10L19/04 ,  H03M3/00

    CPC分类号： G10L19/032 ,  G10L19/005 ,  G10L19/04 ,  G10L25/78 ,  H03M3/424 ,  H03M3/428 ,  H03M3/458 ,  H03M3/466 ,  H03M3/468 ,  H03M5/04

    摘要： A system may include a delta-sigma analog-to-digital converter and a digital compression circuit. The delta-sigma analog-to-digital converter may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal, a multi-bit quantizer configured to quantize the intermediate signal into an uncompressed digital output signal, and a feedback digital-to-analog converter having a feedback output configured to generate a feedback output signal responsive to the uncompressed digital output signal in order to combine the input signal and the feedback output signal at the loop filter input. The digital compression circuit may be configured to receive the uncompressed digital output signal and compress the uncompressed digital output signal into a compressed digital output signal having fewer quantization levels than that of the uncompressed digital output signal.