公开(公告)号：US12294474B2

公开(公告)日：2025-05-06

申请号：US18142977

申请日：2023-05-03

Applicant: Cadence Design Systems, Inc.

Inventor： Ehud Nir

IPC: H04L25/03 ,  H04L27/06 ,  H04L25/49

Abstract: Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.

公开(公告)号：US12287369B1

公开(公告)日：2025-04-29

申请号：US18364064

申请日：2023-08-02

Applicant: Cadence Design Systems, Inc.

Inventor： Patrick Murphy ,  Cornelius O'Shea ,  Joe Canning ,  Dariusz Piotr Palubiak ,  Vitali Karasenko

IPC: G01R31/3185

Abstract: Embodiments include herein are directed towards various circuit topologies. A self-correcting latch circuit may include a plurality of memory loops, a plurality of clock inputs, a plurality of data inputs, and a plurality of outputs. Each of the plurality of memory loops may be configured to store data in parallel.

公开(公告)号：US12242784B1

公开(公告)日：2025-03-04

申请号：US17490378

申请日：2021-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Shadi Saba ,  Roque Alejandro Arcudia Hernandez ,  Uyen Huynh Ha Nguyen ,  Pedro Eugênio Rocha Medeiros ,  Claire Liyan Ying

IPC: G06F30/333 ,  G06N5/022

Abstract: An approach is disclosed herein a sequence generation ecosystem using machine learning. The approach disclosed herein is a new approach to sequence generation in the context of validation that relies on machine learning to explore and identify ways to achieve different states. In particular, the approach divides the valid operations into different respective actions and action sequences. These actions are selected by machine learning models as they are being trained using online inference reinforcement learning. This online inference also is likely to result in the discovery of new states. Each state that has been identified is then used as a target to train a respective machine learning model. As part of this process a representation of all the states and actions or sequences of actions executed to reach those states is created. This representation, the respective machine learning models, or a combination thereof can then be used to generate different test sequences.

公开(公告)号：US12212315B1

公开(公告)日：2025-01-28

申请号：US18093281

申请日：2023-01-04

Applicant: Cadence Design Systems, Inc.

Inventor： Vinod Kumar

IPC: G11C5/14 ,  H03K3/011 ,  H03K17/687 ,  G11C11/4093

Abstract: Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.

公开(公告)号：US12184286B1

公开(公告)日：2024-12-31

申请号：US17831685

申请日：2022-06-03

Applicant: Cadence Design Systems, Inc.

Inventor： Prakash Kumar Lenka ,  Hari Anand Ravi ,  Jitendra Kumar Yadav

IPC: H03K5/00 ,  G01R29/02 ,  H03K3/017 ,  H03K5/24

Abstract: The present disclosure describes a circuit that may include a first amplifier portion configured to receive a first input signal corresponding to a first clock signal and a second input signal corresponding to a second clock signal. The circuit may include a first amplifier of the first amplifier portion. The first amplifier may be configured to receive a first amplifier input signal and a second amplifier input signal. The circuit may include a second amplifier portion configured to receive a first output signal from the first amplifier portion. In a first mode, the first amplifier input signal may be based upon the second input signal and the second amplifier input signal may be based upon the first input signal. In a second mode, the first amplifier input signal may be based upon the first input signal and the second amplifier input signal may be based upon the second input signal.

公开(公告)号：US12182613B1

公开(公告)日：2024-12-31

申请号：US17245506

申请日：2021-04-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Chandra Prakash Manglani ,  Amit Khurana ,  Sunil Prasad Todi

IPC: G06F30/31 ,  G06F3/06 ,  G06F9/48

Abstract: A system for generating a single design data file may include a processor and a memory. The processor may obtain design data including a plurality of design units. The processor may determine a first order of the plurality of design units. The processor may translate each of the plurality of design units into a corresponding file fragment by executing multiple threads of a first process. The processor may aggregate each of the plurality of file fragments into the single design data file in the first order by executing a second process in parallel to the first process.

公开(公告)号：US12182485B1

公开(公告)日：2024-12-31

申请号：US16209885

申请日：2018-12-04

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Christopher Coffman ,  Hitesh Gannu

IPC: G06F30/33 ,  G06F9/455 ,  G06F30/331 ,  G06F30/3323 ,  G06F30/398 ,  G06F115/02 ,  G06F117/08

Abstract: A shared memory is provided between simulation processors and emulation processors within an emulation chip. The shared memory is configured to enable the simulation processors and the emulation processors to exchange simulation data and emulation data respectively with each other during simulation and emulation operations. The simulation processors and the emulation processors may update their respective simulation and emulation operations in response to the simulation data and the emulation data exchanged via the shared memory.

公开(公告)号：US12141233B1

公开(公告)日：2024-11-12

申请号：US16587790

申请日：2019-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Marco Tony Lloyd Kassis ,  Mina Adel Aziz Farhan ,  Joel Reuben Phillips

IPC: G06F18/214 ,  G06F17/12 ,  G06F17/14 ,  G06N20/00

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with an MOR-based envelope Fourier technique. Multiple training models may be determined at multiple time points for an electronic circuit by using at least the MOR-based envelope Fourier technique that comprises a harmonic balance technique. A training model of the multiple training models may be reduced into a reduced order training model in a reduced order space at least by applying at least model order reduction of the MOR-based envelope Fourier technique to the training model. A time varying system may be determined for the electronic circuit based by using at least the reduced order training model.

公开(公告)号：US12099791B1

公开(公告)日：2024-09-24

申请号：US17490496

申请日：2021-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Shadi Saba ,  Roque Alejandro Arcudia Hernandez ,  Uyen Huynh Ha Nguyen ,  Pedro Eugênio Rocha Medeiros ,  Claire Liyan Ying ,  Ruozhi Zhang ,  Gustavo Emanuel Faria Araujo

IPC: G06F30/333

CPC classification number: G06F30/333

Abstract: An approach is disclosed herein for test sequence processing that is applicable to machine learning model generated test sequences as disclosed herein. The test sequence processing includes classification, grouping, and filtering. The classification is generated based on the execution of the test sequences. The grouping is performed based on information captured during the classification of the test sequences. The filtering is performed on a group by group basis to remove redundant test sequences.

公开(公告)号：US12086529B1

公开(公告)日：2024-09-10

申请号：US17691974

申请日：2022-03-10

Applicant: Cadence Design Systems, Inc.

Inventor： Igor Keller ,  Eric K. Anderson ,  Yang Gao

IPC: G06F30/398 ,  G06F30/3315 ,  G06F119/02

CPC classification number: G06F30/398 ,  G06F30/3315 ,  G06F2119/02

Abstract: Various embodiments provide for using a timing-based yield calculation to modify a circuit design, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a timing-based yield calculation to modify one or more portions of the circuit design to improve timing of the circuit design (e.g., slack, slew, delay, etc.), the timing-based yield calculation of the circuit design, or both.