公开(公告)号：US20110108994A1

公开(公告)日：2011-05-12

申请号：US12841321

申请日：2010-07-22

Applicant: Ming-Chung LIANG ,  Chii-Ping CHEN

Inventor： Ming-Chung LIANG ,  Chii-Ping CHEN

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76802 ,  H01L21/3212 ,  H01L21/76829 ,  H01L21/7684 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00013 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer.

Abstract translation: 一种用于形成集成电路的方法包括在晶体管的栅极上形成第一介电层。 在第一介电层上形成蚀刻停止层。 通过第一介电层和蚀刻停止层形成开口，暴露晶体管的源极/漏极（S / D）区域。 在开口中形成金属层，与晶体管的S / D区接触。 金属层具有至少部分地基本上与蚀刻停止层的第一顶表面平齐的表面。 形成镶嵌结构并与金属层耦合。

公开(公告)号：US06949007B1

公开(公告)日：2005-09-27

申请号：US10930886

申请日：2004-08-31

Applicant: Kuo-Hwa Wang ,  Chii-Ping Chen

Inventor： Kuo-Hwa Wang ,  Chii-Ping Chen

IPC: B24B1/00 ,  B24B49/00

CPC classification number: B24B37/013 ,  B24B49/00

Abstract: A fabricating system. A processing tool executes a film removal process on a wafer using a chemical mechanism. A metrology tool monitors surface characteristics of the wafer to obtain a measured film thickness thereof before and after a first removal process, wherein the first removal process lasts a first processing duration. The controller, coupled to the processing and metrology tools, determines whether the difference between the measured film thickness and a preset film thickness exceeds a preset value, and determines a second processing duration of a second removal process according to the measured and preset film thickness and the first processing duration.

Abstract translation: 制造系统。 处理工具使用化学机构在晶片上执行膜去除处理。 测量工具监测晶片的表面特性，以在第一去除过程之前和之后获得其测量的膜厚度，其中第一去除过程持续第一处理持续时间。 耦合到处理和计量工具的控制器确定测量的膜厚度和预设膜厚度之间的差是否超过预设值，并且根据测量和预设的膜厚确定第二去除处理的第二处理持续时间，以及 第一个处理时间。

公开(公告)号：US09257279B2

公开(公告)日：2016-02-09

申请号：US13434366

申请日：2012-03-29

Applicant: Jiing-Feng Yang ,  Chii-Ping Chen ,  Dian-Hau Chen

Inventor： Jiing-Feng Yang ,  Chii-Ping Chen ,  Dian-Hau Chen

IPC: H01L21/32 ,  H01L21/337 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/0337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32139

Abstract: A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask.

Abstract translation: 提供了一种形成半导体器件的方法，以及由此形成的产品。 该方法包括使用例如双图案化或多图案化技术在掩模层中形成图案。 将面罩处理成平滑或圆形的尖角。 在其中在掩模中形成正型图案的实施例中，处理可以包括等离子体工艺或各向同性的湿蚀刻。 在其中在掩模中形成阴性图案的实施例中，治疗可以包括在掩模图案上形成共形层。 保形层将具有使锐角四舍五入的效果。 可以使用其它技术来平滑或圆形掩模的角部。

公开(公告)号：US20130260563A1

公开(公告)日：2013-10-03

申请号：US13434366

申请日：2012-03-29

Applicant: Jiing-Feng Yang ,  Chii-Ping Chen ,  Dian-Hau Chen

Inventor： Jiing-Feng Yang ,  Chii-Ping Chen ,  Dian-Hau Chen

IPC: H01L21/32

CPC classification number: H01L21/0337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32139

Abstract: A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask.

Abstract translation: 提供了一种形成半导体器件的方法，以及由此形成的产品。 该方法包括使用例如双图案化或多图案化技术在掩模层中形成图案。 将面罩处理成平滑或圆形的尖角。 在其中在掩模中形成正型图案的实施例中，处理可以包括等离子体工艺或各向同性的湿蚀刻。 在其中在掩模中形成阴性图案的实施例中，治疗可以包括在掩模图案上形成共形层。 保形层将具有使锐角四舍五入的效果。 可以使用其它技术来平滑或圆形掩模的角部。

公开(公告)号：US20130256902A1

公开(公告)日：2013-10-03

申请号：US13438565

申请日：2012-04-03

Applicant: Lee-Chung LU ,  Wen-Hao CHEN ,  Yuan-Te HOU ,  Fang-Yu FAN ,  Yu-Hsiang KAO ,  Dian-Hau CHEN ,  Shyue-Shyh LIN ,  Chii-Ping CHEN

Inventor： Lee-Chung LU ,  Wen-Hao CHEN ,  Yuan-Te HOU ,  Fang-Yu FAN ,  Yu-Hsiang KAO ,  Dian-Hau CHEN ,  Shyue-Shyh LIN ,  Chii-Ping CHEN

IPC: H01L23/48

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

Abstract translation: 一种互连结构，其包括在衬底上的底层，其中底层包括至少一个底层线和至少一个底层通孔。 互连结构还包括在底层上的过渡层，其中过渡层包括至少一个过渡层线和至少一个过渡层通孔。 互连结构还包括过渡层上的顶层，其中顶层包括至少一个顶层线和至少一个顶层通孔。 所述至少一个过渡层通孔具有比所述至少一个顶层通孔的横截面面积小至少30％的横截面面积。

公开(公告)号：US08499261B2

公开(公告)日：2013-07-30

申请号：US13474865

申请日：2012-05-18

Applicant: Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Chii-Ping Chen ,  Jiing-Feng Yang

Inventor： Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Chii-Ping Chen ,  Jiing-Feng Yang

IPC: G06F17/50

CPC classification number: G03F7/70466 ,  G03F1/70

Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.

Abstract translation: 提供一种用于制造半导体器件的装置。 该装置包括第一光掩模和第二光掩模。 第一光掩模在其上具有多个第一特征，并且第一光掩模具有第一全局图案密度。 第二光掩模在其上具有多个第二特征，并且第二光掩模具有第二全局图案密度。 多个第一和第二特征共同地限定了半导体器件的层的布局图像。 第一和第二全局图案密度具有预定比例。

公开(公告)号：US20120227018A1

公开(公告)日：2012-09-06

申请号：US13474865

申请日：2012-05-18

Applicant: Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Chii-Ping Chen ,  Jiing-Feng Yang

Inventor： Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Chii-Ping Chen ,  Jiing-Feng Yang

IPC: G06F17/50

CPC classification number: G03F7/70466 ,  G03F1/70

Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.

Abstract translation: 提供一种用于制造半导体器件的装置。 该装置包括第一光掩模和第二光掩模。 第一光掩模在其上具有多个第一特征，并且第一光掩模具有第一全局图案密度。 第二光掩模在其上具有多个第二特征，并且第二光掩模具有第二全局图案密度。 多个第一和第二特征共同地限定了半导体器件的层的布局图像。 第一和第二全局图案密度具有预定比例。

公开(公告)号：US08196072B2

公开(公告)日：2012-06-05

申请号：US12750873

申请日：2010-03-31

Applicant: Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Chii-Ping Chen ,  Jiing-Feng Yang

Inventor： Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Chii-Ping Chen ,  Jiing-Feng Yang

IPC: G06F17/50

CPC classification number: G03F7/70466 ,  G03F1/70

Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.

Abstract translation: 提供一种用于制造半导体器件的装置。 该装置包括第一光掩模和第二光掩模。 第一光掩模在其上具有多个第一特征，并且第一光掩模具有第一全局图案密度。 第二光掩模在其上具有多个第二特征，并且第二光掩模具有第二全局图案密度。 多个第一和第二特征共同地限定了半导体器件的层的布局图像。 第一和第二全局图案密度具有预定比例。

公开(公告)号：US20100308469A1

公开(公告)日：2010-12-09

申请号：US12478619

申请日：2009-06-04

Applicant: Hsin-Yi Tsai ,  Chih-Hao Chen ,  Ming-Chung Liang ,  Chii-Ping Chen ,  Lai Chien Wen ,  Yuh-Jier Mii

Inventor： Hsin-Yi Tsai ,  Chih-Hao Chen ,  Ming-Chung Liang ,  Chii-Ping Chen ,  Lai Chien Wen ,  Yuh-Jier Mii

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.

Abstract translation: 本公开提供一种半导体器件，其包括：衬底; 第一导电线，位于所述衬底上并且沿着第一轴线延伸，所述第一导电线具有第一长度和第一宽度，所述第一长度沿着所述第一轴线被测量; 第二导电线，位于第一导电线之上并沿着不同于第一轴的第二轴延伸，第二导线具有第二长度和第二宽度，第二长度沿第二轴线测量; 以及耦合所述第一和第二导线的通孔，所述通孔具有接触所述第二导电线的上表面和接触所述第一导线的下表面。 通孔在上表面具有大致直边，直边沿第二轴线延伸并与第二导线基本对准。

公开(公告)号：US06756309B1

公开(公告)日：2004-06-29

申请号：US10356247

申请日：2003-01-30

Applicant: Chii-Ping Chen ,  Wen-Chen Chien ,  Ching-Ming Tsai

Inventor： Chii-Ping Chen ,  Wen-Chen Chien ,  Ching-Ming Tsai

IPC: H01L21302

CPC classification number: H01L21/7684

Abstract: A method for achieving a predetermined electrical resistance of a semiconductor device metal line in a CMP process including providing a semiconductor process wafer comprising at least one dielectric layer for etching an opening through a thickness of the at least one dielectric layer; measuring a thickness of the at least one dielectric layer prior to etching the opening; etching the opening through a thickness of the at least one dielectric layer; measuring at least one dimension of the opening from which at least an opening depth is determined; forming a metal layer to fill the opening; and, performing a chemical mechanical polish (CMP) process to remove at least the metal layer overlying the opening level to form a metal filled opening according to a projected metal filled opening electrical resistance.

Abstract translation: 一种用于在CMP工艺中实现半导体器件金属线的预定电阻的方法，包括提供半导体工艺晶片，所述半导体工艺晶片包括至少一个电介质层，用于通过所述至少一个电介质层的厚度蚀刻开口; 在蚀刻所述开口之前测量所述至少一个电介质层的厚度; 通过所述至少一个介电层的厚度蚀刻所述开口; 测量所述开口的至少一个尺寸，至少确定至少一个开口深度; 形成金属层以填充开口; 并且进行化学机械抛光（CMP）工艺，以至少去除覆盖开口水平面的金属层，以根据突出的金属填充开口电阻形成金属填充开口。