公开(公告)号：US20080136427A1

公开(公告)日：2008-06-12

申请号：US11567449

申请日：2006-12-06

Applicant: Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

Inventor： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

IPC: G01R31/26 ,  G01R1/067

CPC classification number: G01R31/31723 ,  G01R31/2884 ,  G01R31/31926

Abstract: The invention is directed to an on-chip probing apparatus. In accordance with an embodiment of the present invention, the on-chip probing apparatus includes: a plurality of switches on a chip; a plurality of externally accessible probe points on the chip; and a multiplexer for controlling the plurality of switches to selectively couple an output signal of the chip to one of the plurality of probe points.

Abstract translation: 本发明涉及片上探测装置。 根据本发明的实施例，片上探测装置包括：芯片上的多个开关; 芯片上的多个外部可访问的探针点; 以及多路复用器，用于控制所述多个开关以选择性地将所述芯片的输出信号耦合到所述多个探针点中的一个。

公开(公告)号：US07533458B1

公开(公告)日：2009-05-19

申请号：US12174810

申请日：2008-07-17

Applicant: Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

Inventor： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

IPC: H05K3/36

CPC classification number: H05K1/024 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T156/1013

Abstract: Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.

Abstract translation: 降低高速数字系统噪声耦合的方法和系统。 示例性实施例包括一种方法，包括将多个高速信号迹线蚀刻到芯绝缘层上，在多个高速信号迹线的相应侧上形成沟槽，从而去除与多个高速信号迹线相邻的绝缘材料，并形成 具有剩余绝缘材料的基座，多个高速信号迹线设置在剩余绝缘材料上并耦合到剩余的绝缘材料上，将高速信号迹线上的预预处理材料耦合，去除与沟槽相邻的预浸料， 将材料与高速信号迹线对准，并且将芯层加热并压制到预浸层，以及将预浸层加热和压制到芯绝缘层。

公开(公告)号：US20080112503A1

公开(公告)日：2008-05-15

申请号：US11560257

申请日：2006-11-15

Applicant: Daniel N. De Araujo ,  Moises Cases ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

Inventor： Daniel N. De Araujo ,  Moises Cases ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

IPC: H04L25/03

CPC classification number: H04L25/0264 ,  H04L25/0286

Abstract: An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.

Abstract translation: 公开了用于通信信道中的动态相位均衡的装置，系统和方法。 发射机历史模块从通过通信信道发送的数据流存储多个比特。 发射机检测模块检测在数据流中前面的第一值的前转换比特的第一值的至少一个比特，然后跟随具有第二值的转换比特。 驾驶员模块通过驱动通信信道来发送数据流。 转换模块在预转换位的位时间间隔期间将通信通道预驱动到转换位的第二电压。

公开(公告)号：US08289101B2

公开(公告)日：2012-10-16

申请号：US11737196

申请日：2007-04-19

Applicant: Justin P. Bandholz ,  Moises Cases ,  Robert J. Christopher ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

Inventor： Justin P. Bandholz ,  Moises Cases ,  Robert J. Christopher ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

IPC: H03H7/38

CPC classification number: H05K1/0237 ,  H04L25/028 ,  H04L25/0288 ,  H04L25/03343 ,  H05K1/14 ,  H05K1/181 ,  H05K2201/044 ,  H05K2201/1006

Abstract: Embodiments of the present invention address deficiencies of the art in respect to via structure utilization in a PCB design and provide a novel and non-obvious method, system and computer program product for impedance discontinuity remediation for via stubs and connectors in a PCB. In one embodiment a method for impedance discontinuity remediation in a PCB can be provided. The method can include configuring a pre-distortion filter to negate an impedance discontinuity in an electrical signal caused by a transmission line with one of a via stub or a connector. The method further can include pre-distortion filtering an electrical signal before transmitting the electrical signal over the transmission line. Finally, the method can include transmitting the pre-distortion filtered electrical signal over the transmission line.

Abstract translation: 本发明的实施例解决了PCB设计中的通孔结构利用方面的技术缺陷，并且提供了一种用于PCB中经由短线和连接器的阻抗不连续修复的新颖且非显而易见的方法，系统和计算机程序产品。 在一个实施例中，可以提供PCB中阻抗不连续修复的方法。 该方法可以包括配置预失真滤波器以消除由具有通孔短路或连接器之一的传输线引起的电信号中的阻抗不连续性。 该方法还可以包括在通过传输线路传输电信号之前对电信号进行预失真滤波。 最后，该方法可以包括通过传输线传输预失真滤波的电信号。

公开(公告)号：US07759958B2

公开(公告)日：2010-07-20

申请号：US11859540

申请日：2007-09-21

Applicant: Moises Cases ,  Shiva R. Dasari ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Nam H. Pham

Inventor： Moises Cases ,  Shiva R. Dasari ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Nam H. Pham

IPC: G01R31/02 ,  G06F17/50

CPC classification number: G06F11/24 ,  G11C5/04 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/50 ,  G11C2029/5004

Abstract: An apparatus, system, and method are disclosed for integrating component testing. A voltage module modifies a reference voltage integral to an electronic device to a plurality of reference voltage values. A test module tests a component of the electronic device at each of the plurality of reference voltage values. In addition, the test module determines a voltage range for the component, wherein the voltage range comprises voltage values between a high voltage failure and a low voltage failure. An optimization module sets the reference voltage value to within the voltage range.

Abstract translation: 公开了用于集成部件测试的装置，系统和方法。 电压模块将对电子设备积分的参考电压修改为多个参考电压值。 测试模块在多个参考电压值中的每一个测试电子设备的组件。 此外，测试模块确定组件的电压范围，其中电压范围包括高电压故障和低电压故障之间的电压值。 优化模块将参考电压值设置在电压范围内。

公开(公告)号：US20090107705A1

公开(公告)日：2009-04-30

申请号：US11924416

申请日：2007-10-25

Applicant: Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

Inventor： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

IPC: H05K3/00 ,  H05K1/03

CPC classification number: H05K1/024 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T156/1013

Abstract: Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.

Abstract translation: 降低高速数字系统噪声耦合的方法和系统。 示例性实施例包括一种方法，包括将多个高速信号迹线蚀刻到芯绝缘层上，在多个高速信号迹线的相应侧上形成沟槽，从而去除与多个高速信号迹线相邻的绝缘材料，并形成 具有剩余绝缘材料的基座，多个高速信号迹线设置在剩余绝缘材料上并耦合到剩余的绝缘材料上，将高速信号迹线上的预预处理材料耦合，去除与沟槽相邻的预浸料， 将材料与高速信号迹线对准，并且将芯层加热并压制到预浸层，以及将预浸层加热和压制到芯绝缘层。

公开(公告)号：US20090106976A1

公开(公告)日：2009-04-30

申请号：US12174810

申请日：2008-07-17

Applicant: Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

Inventor： Moises Cases ,  Bradley D. Herrman ,  Kent B. Howieson ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham ,  Caleb J. Wesley

IPC: H05K3/02 ,  B29C53/00

CPC classification number: H05K1/024 ,  H05K3/4611 ,  H05K3/4697 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2203/063 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T156/1013

Abstract: Methods and systems for reducing noise coupling in high-speed digital systems. Exemplary embodiments include a method, including etching a plurality of high speed signal traces onto a core insulating layer, forming trenches on respective sides of the plurality of high speed signal traces, thereby removing insulating material adjacent to the plurality of high speed signal traces and forming pedestals having remaining insulating material, the plurality of high speed signal traces disposed on and coupled to the remaining insulating material, coupling pre-preg material on the high speed signal traces, removing the pre-preg material adjacent the trenches, thereby retaining the pre-preg material aligned with the high speed signal traces, and heating and pressing a core layer to the pre-preg layer, and heating and pressing the pre-preg layer to the core insulating layer.

Abstract translation: 降低高速数字系统噪声耦合的方法和系统。 示例性实施例包括一种方法，包括将多个高速信号迹线蚀刻到芯绝缘层上，在多个高速信号迹线的相应侧上形成沟槽，从而去除与多个高速信号迹线相邻的绝缘材料，并形成 具有剩余绝缘材料的基座，多个高速信号迹线设置在剩余绝缘材料上并耦合到剩余的绝缘材料上，将高速信号迹线上的预预处理材料耦合，去除与沟槽相邻的预浸料， 将材料与高速信号迹线对准，并且将芯层加热并压制到预浸层，以及将预浸层加热和压制到芯绝缘层。

公开(公告)号：US20090049414A1

公开(公告)日：2009-02-19

申请号：US11840075

申请日：2007-08-16

Applicant: Bhyrav M. MUTNURY ,  Moises Cases ,  Wallace G. Tuten ,  Erdem Matoglu

Inventor： Bhyrav M. MUTNURY ,  Moises Cases ,  Wallace G. Tuten ,  Erdem Matoglu

IPC: G06F17/50 ,  H05K1/11

CPC classification number: H05K3/0005 ,  G06F17/5068 ,  H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09636

Abstract: Reducing via stub resonance in printed circuit boards. In one aspect, a method for reducing via stub resonance in a circuit board includes determining that resonance exists for a signal to be transmitted through a signal via extending across a plurality of layers in the circuit board. The resonance is caused by a via stub of the signal via, the via stub extending past a layer connected to the signal via. A location is determined for a ground via to be placed relative to the signal via, the location of the ground via being determined based on reducing the resonance for the signal to be transmitted in the signal via.

Abstract translation: 通过印刷电路板中的短截线减少。 在一个方面，一种用于减少电路板中的通路短路谐振的方法包括确定通过延伸穿过电路板中的多个层的通过信号传输的信号的共振。 谐振是由信号通孔的通孔短路引起的，通孔短路延伸通过与信号通孔连接的层。 确定相对于信号通路放置的地面通路的位置，基于通过减少在信号通道中要发送的信号的谐振来确定地面的位置。

公开(公告)号：US20070257699A1

公开(公告)日：2007-11-08

申请号：US11407814

申请日：2006-04-20

Applicant: Moises Cases ,  Daniel De Araujo ,  Erdem Matoglu ,  Pravin Patel ,  Nam Pham

Inventor： Moises Cases ,  Daniel De Araujo ,  Erdem Matoglu ,  Pravin Patel ,  Nam Pham

IPC: H03K17/16

CPC classification number: G11C5/04 ,  G11C5/063

Abstract: A multi-memory module circuit topology is disclosed that includes a memory controller, a plurality of memory modules connected to the memory controller through a memory bus, and a resonator connected to the plurality of memory modules in a starburst topology. A method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing a plurality of memory modules connected to a memory controller through a memory bus, selecting a starburst topology, and connecting a resonator to the plurality of memory module in dependence upon the selected starburst topology. An additional method for reducing impedance discontinuities in a multi-memory module circuit is disclosed that includes providing by a resonator a predetermined discontinuity reducing impedance at a predetermined location in the multi-memory module circuit between at least two memory modules, the multi-memory module circuit having a plurality of components of logically arranged around the predetermined location.

Abstract translation: 公开了一种多存储器模块电路拓扑，其包括存储器控制器，通过存储器总线连接到存储器控制器的多个存储器模块，以及以星爆拓扑连接到多个存储器模块的谐振器。 公开了一种用于减少多存储器模块电路中的阻抗不连续性的方法，其包括通过存储器总线提供连接到存储器控制器的多个存储器模块，选择星爆拓扑，并且依次将谐振器连接到多个存储器模块 在选定的星爆拓扑上。 公开了一种用于减少多存储器模块电路中的阻抗不连续性的附加方法，其包括由谐振器在至少两个存储器模块之间的多存储器模块电路中的预定位置处提供预定的不连续性减小阻抗，所述多存储器模块 电路具有围绕预定位置逻辑布置的多个部件。

公开(公告)号：US20070178289A1

公开(公告)日：2007-08-02

申请号：US11340907

申请日：2006-01-27

Applicant: Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Pravin Patel ,  Nam H. Pham ,  Joffre A. Ratcliffe

Inventor： Moises Cases ,  Daniel N. de Araujo ,  Bradley D. Herrman ,  Erdem Matoglu ,  Pravin Patel ,  Nam H. Pham ,  Joffre A. Ratcliffe

IPC: B32B3/00

CPC classification number: B32B17/04 ,  H05K1/0248 ,  H05K1/025 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09227 ,  Y10T428/24917

Abstract: An electronic system includes a circuit board formed from a composite material. The composite material includes fibers embedded within a substrate and the fibers are oriented substantially orthogonal to one another. A plurality of traces are formed on the board, and the plurality of traces are oriented relative to at least one of the fibers at an angle between about 17.5° and about 27.5° or between about 20.0° and about 25.0°. A pair of the traces are oriented substantially orthogonal to one another, and a pair of the traces are oriented relative to one another at an angle of about 45.0°. The fibers are fiberglass, and the substrate is an epoxy resin. The fibers have a different dielectric constant than the substrate.

Abstract translation: 电子系统包括由复合材料形成的电路板。 复合材料包括嵌入基片内的纤维，纤维彼此基本正交。 在板上形成多个迹线，并且多个迹线相对于至少一个光纤以约17.5°至约27.5°之间的角度或约20.0°至约25.0°的角度定向。 一对迹线基本上彼此正交地定向，并且一对迹线以大约45.0°的角度相对于彼此定向。 纤维是玻璃纤维，基材是环氧树脂。 纤维的介电常数不同于基材。