公开(公告)号：US09689009B2

公开(公告)日：2017-06-27

申请号：US13278106

申请日：2011-10-20

申请人： Jin Sook Chang ,  Jae Hyun Jo ,  Hyun Ae Bae ,  Byeong Cheol Song ,  Sol Kim ,  Hye Won Kim ,  Hye Won Um ,  Sung Hoo Jhon ,  Yong Uk Shin ,  Eun Bin Yang ,  Kyoung Min Lee ,  Soo An Shin

发明人： Jin Sook Chang ,  Jae Hyun Jo ,  Hyun Ae Bae ,  Byeong Cheol Song ,  Sol Kim ,  Hye Won Kim ,  Hye Won Um ,  Sung Hoo Jhon ,  Yong Uk Shin ,  Eun Bin Yang ,  Kyoung Min Lee ,  Soo An Shin

IPC分类号： C12P13/12 ,  C12P13/06 ,  C12N9/10 ,  C12N9/16 ,  C12N15/70 ,  C12N15/77

CPC分类号： C12P13/12 ,  C12N9/1085 ,  C12N9/16 ,  C12N15/70 ,  C12N15/77 ,  C12P13/06 ,  C12Y205/01065 ,  C12Y301/03003

摘要： The present invention provides methods for the production of cysteine or derivates thereof by culturing a microorganism having reduced activity of endogenous phosphoserine phosphatase and the activity of PhnC, PhnD, and PhnE is reduced, and enhanced activity of phosphoglycerate dehydrogenase and/or phosphoserine aminotransferase. The O-phosphoserine produced by such an organism can then be reacted with a sulfide in the presence of a sulfydrylase or a microorganism expressing a sulfhydrylase to produce cysteine or a derivative thereof. Microorganisms having these reduced and enhanced properties noted above are also provided herein.

公开(公告)号：US09508425B2

公开(公告)日：2016-11-29

申请号：US13167920

申请日：2011-06-24

申请人： Wei Lu ,  Sung Hyun Jo

发明人： Wei Lu ,  Sung Hyun Jo

IPC分类号： H01L47/00 ,  G11C11/56 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： G11C11/5685 ,  G11C13/0007 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675

摘要： A non-volatile memory device structure. The non-volatile memory device structure comprises a first electrode formed from a first metal material, a resistive switching element overlying the first electrode. The resistive switching element comprises a metal oxide material characterized by one or more oxygen deficient sites. The device includes a second electrode overlying the resistive switching layer, the second electrode being formed from a second metal material. The second electrode is made from a noble metal. The one or more oxygen deficient sites are caused to migrate from one of the first electrode or the second electrode towards the other electrode upon a voltage applied to the first electrode or the second electrode. The device can have a continuous change in resistance upon applying a continuous voltage ramp, suitable for an analog device. Alternatively, the device can have a sharp change in resistance upon applying the continuous voltage ramp, suitable for a digital device.

摘要翻译： 非易失性存储器件结构。 非易失性存储器件结构包括由第一金属材料形成的第一电极，覆盖第一电极的电阻式开关元件。 电阻式开关元件包括以一个或多个缺氧部位为特征的金属氧化物材料。 该器件包括覆盖电阻开关层的第二电极，第二电极由第二金属材料形成。 第二电极由贵金属制成。 当施加到第一电极或第二电极的电压时，使一个或多个缺氧部位从第一电极或第二电极中的一个迁移到另一个电极。 当施加适用于模拟装置的连续电压斜坡时，该装置可以具有连续的电阻变化。 或者，在施加适用于数字设备的连续电压斜坡时，该装置可以具有急剧的电阻变化。

公开(公告)号：US08907317B2

公开(公告)日：2014-12-09

申请号：US13291094

申请日：2011-11-07

申请人： Wei Lu ,  Sung Hyun Jo ,  Kuk-Hwan Kim

发明人： Wei Lu ,  Sung Hyun Jo ,  Kuk-Hwan Kim

IPC分类号： H01L29/06 ,  H01L21/82 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C11/56 ,  B82Y10/00

CPC分类号： H01L45/1253 ,  B82Y10/00 ,  B82Y30/00 ,  G11C11/5614 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/005 ,  G11C2013/0071 ,  G11C2213/11 ,  G11C2213/33 ,  G11C2213/77 ,  G11C2213/81 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/148 ,  H01L45/1608 ,  H01L45/1675

摘要： The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.

摘要翻译： 本申请描述了一种交叉开关存储器阵列。 存储器阵列包括第一材料的平行纳米线的第一阵列和第二材料的平行纳米线的第二阵列。 第一和第二阵列彼此成一角度定向。 阵列还包括布置在第一材料的纳米线和第二材料的纳米线之间的两个阵列的每个交叉处的非晶硅的多个纳米结构。 纳米结构与第一和第二材料的纳米线一起形成电阻记忆单元。

公开(公告)号：US20140205488A1

公开(公告)日：2014-07-24

申请号：US13747451

申请日：2013-01-22

申请人： Hyun Jo Jun ,  Narayan Subramaniam Pottore ,  Nina Michailovna Ponstein ,  Oleg N. Yakubovsky

发明人： Hyun Jo Jun ,  Narayan Subramaniam Pottore ,  Nina Michailovna Ponstein ,  Oleg N. Yakubovsky

IPC分类号： C22C38/14 ,  C22C38/08 ,  C22C38/00 ,  C22C38/04 ,  C22C38/02 ,  C22C38/12 ,  C22C38/06

CPC分类号： C22C38/14 ,  C22C38/00 ,  C22C38/001 ,  C22C38/02 ,  C22C38/04 ,  C22C38/06 ,  C22C38/08 ,  C22C38/12

摘要： A cold rolled, annealed TRIP steel sheet which has a composition including (in wt. %): C: 0.1-0.3; Mn: 4-10, Al: 0.05-5, Si: 0.05-5; and Nb: 0.008-0.1, the remainder being iron and inevitable residuals. The cold rolled sheet has an ultimate tensile strength of at least 1000 MPa, and a total elongation of at least 15%. The cold rolled sheet may have at least 20% retained austenite in its microstructure and may have greater than 50% lath-type annealed ferrite structure. The cold rolled sheet may have an ultra fine grain size of less than 5 micron for the retained austenite and ferrite.

摘要翻译： 冷轧退火TRIP钢板，其组成包括（重量％）：C：0.1-0.3; Mn：4-10，Al：0.05-5，Si：0.05-5; 和Nb：0.008-0.1，其余为铁和不可避免的残留物。 冷轧板具有至少1000MPa的极限拉伸强度和至少15％的总伸长率。 冷轧板在其微结构中可具有至少20％的残余奥氏体，并且可具有大于50％的板条型退火铁素体结构。 对于残留奥氏体和铁素体，冷轧板可以具有小于5微米的超细晶粒度。

公开(公告)号：US20140099898A1

公开(公告)日：2014-04-10

申请号：US14104781

申请日：2013-12-12

申请人： Ka-won CHEON ,  Jae-uk Han ,  Ji-su Jung ,  Hyun-koo Kwak ,  Sung-joon Park ,  Soo-hyun Jo

发明人： Ka-won CHEON ,  Jae-uk Han ,  Ji-su Jung ,  Hyun-koo Kwak ,  Sung-joon Park ,  Soo-hyun Jo

IPC分类号： H04W4/00

CPC分类号： H04W4/80 ,  G06F3/017 ,  H04M1/7253 ,  H04M1/72558 ,  H04M2250/12 ,  H04M2250/64

摘要： A terminal device and a data transceiving method are provided. The terminal device includes a sensing unit which senses a momentum of the terminal device, an interface unit which receives a momentum from at least one external device, and a control unit which performs one of a data receiving operation, a data transmitting operation, and a data transceiving operation with the at least one external device depending on a comparison value obtained from a comparison of the sensed momentum with the received momentum to allow two devices to exchange data more easily.

摘要翻译： 提供终端设备和数据收发方法。 终端装置包括感测终端装置的动量的感测单元，从至少一个外部装置接收动量的接口单元，以及执行数据接收操作，数据发送操作和数据发送操作之一的控制单元 根据从感测到的动量与接收到的动量的比较获得的比较值，使用至少一个外部设备进行数据收发操作，以允许两个设备更容易地交换数据。

公开(公告)号：US20140036605A1

公开(公告)日：2014-02-06

申请号：US13735814

申请日：2013-01-07

申请人： Wei Lu ,  Sung Hyun Jo

发明人： Wei Lu ,  Sung Hyun Jo

IPC分类号： G11C13/00 ,  H02H9/08

CPC分类号： H01L45/1616 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/33 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/141 ,  H01L45/146 ,  H01L45/148 ,  H02H9/08

摘要： A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided.

公开(公告)号：US08555000B2

公开(公告)日：2013-10-08

申请号：US12761488

申请日：2010-04-16

申请人： Myung Hyun Jo ,  Sungchul Kim ,  Jeonguk Kang

发明人： Myung Hyun Jo ,  Sungchul Kim ,  Jeonguk Kang

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/126

摘要： A data storage device and a data storing method thereof, including first main memories coupled to a plurality of channels, second main memories coupled to the plurality of channels in common, a buffer memory temporarily storing data to be programmed to the first and the second main memories; and a controller configured to program data of victim cache lines from the buffer memory to the second main memories while data of a first victim cache line from the buffer memory is being programmed to the first main memories. The storing method includes that a victim cache line is selected based on cost-based page replacement.

摘要翻译： 一种数据存储设备及其数据存储方法，包括耦合到多个通道的第一主存储器，共同耦合到多个通道的第二主存储器，临时存储要编程到第一和第二主器件的数据的缓冲存储器 回忆 以及控制器，被配置为将来自缓冲存储器的第一受害者高速缓存行的数据正被编程到第一主存储器中，将缓冲存储器行的数据从缓冲存储器编程到第二主存储器。 存储方法包括基于成本的页面替换来选择受害者高速缓存行。

公开(公告)号：US08489852B2

公开(公告)日：2013-07-16

申请号：US12815445

申请日：2010-06-15

申请人： Myung-hyun Jo ,  Chan-ik Park

发明人： Myung-hyun Jo ,  Chan-ik Park

IPC分类号： G06F12/00

CPC分类号： G06F12/00 ,  G06F12/0246 ,  G06F2212/7201 ,  Y02D10/13

摘要： A method of manipulating data includes receiving a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The method further includes mapping the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command. A system for manipulating data includes a host and a flash translation layer. The host transmits a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The flash translation layer maps the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command.

公开(公告)号：US08444867B2

公开(公告)日：2013-05-21

申请号：US12582530

申请日：2009-10-20

申请人： Hyun Jo Yang

发明人： Hyun Jo Yang

IPC分类号： C03C25/68

CPC分类号： G03F7/0035 ,  G03F7/2022 ,  H01L21/0274 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

摘要： A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist.

摘要翻译： 在晶片上形成图案的方法包括在晶片的边缘部分形成具有倾斜面的栅栏。 倾斜的表面直接通向晶片的内部。 形成第一光致抗蚀剂层，其延伸以覆盖晶片上的栅栏。 通过在第一光致抗蚀剂层上进行第一曝光和显影来形成第一光致抗蚀剂图案。 使用第一光致抗蚀剂图案和栅栏作为蚀刻掩模执行蚀刻工艺。 通过使用遮光片选择性曝光负性抗蚀剂而形成栅栏，此时形成包括正性抗蚀剂的第一光致抗蚀剂层。

公开(公告)号：USRE44221E1

公开(公告)日：2013-05-14

申请号：US13507529

申请日：2012-07-05

申请人： Hyun Jo Yang

发明人： Hyun Jo Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Provided is a method for verifying a pattern of a semiconductor device. In the method, a designed layout of target patterns is provided, and transferring the designed layout on a wafer to form wafer patterns. Wafer patterns image contour is obtain. The image contour for wafer patterns on the designed layout are matched, After edge differences between the designed layout and the wafer patterns image contour are extracted, a checking layout for detecting wafer pattern defects is obtain by adding the edge differences on the designed layout. Defects on the checking layout is identified to verify the patterns in view of processes before fabrication of a photomask.

摘要翻译： 提供一种用于验证半导体器件的图案的方法。 在该方法中，提供了目标图案的设计布局，并将设计的布局转移到晶片上以形成晶片图案。 获得晶圆图案图像轮廓。 在设计布局上的晶片图案的图像轮廓匹配，提取设计布局和晶片图案图像轮廓之间的边缘差异之后，通过在设计布局上添加边缘差异来获得检测晶片图案缺陷的检查布局。 识别检查布局的缺陷被识别，以鉴于在制作光掩模之前的过程来验证图案。